GENNUM EB1572, Reference Design

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GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
46282 - 1
November 2009
11 of 18
Proprietary & Confidential
4. Board Schematic
Figure 4-1 shows the top level schematic of the GS1572. Figure 4-2 shows the chip level
in more detail.
Figure 4-1: Top Level
GND
GND
SCLK_TCK
C55
100N
GND
IO_VDD
1.8V 1A regulator -
IRU1206-18CY
3.3V 1A regulator -
IRU1206-33CY
VOUT
3
VIN
1
GND
2
GND
4
U19
IRU1206-33CY /SOT-223
VOUT
3
VIN
1
GND
2
GND
4
U20
IRU1206-18CY /SOT-223
GND
IO_VDD
1
1
2
2
3
3
4
4
J1
LP 5.00/4/90
C6
10UF
VCC
TP7
testpt
TP6
testpt
R8
NP
GND_A
C16
NP
GND
R70 0R
Reset Switch
1 2
3 4
5 6
7 8
9 10
JP2
HEADER 5X2
GND
1
2
C56
10U
1
2
C60
10U
VCC
C57
100N
VCC
DATA_IN8
DATA_IN9
C61
100N
GS1572
GS1572
PCLK
F
V
H
SDO
SDOn
DVB_ASI
SD/HDb
SMPTE_BY PASSb
RESET_TRSTb
SCLK_TCK
SDIN_TDI
CSb_TMS
SDOUT_TDO
DATA_IN[19:0]
+3.3V
+1.8V
R12 0R
GND
GND
GND_A
GND
GND_A
Input Power
DATA_IN17
DATA_IN16
DATA_IN12
DATA_IN14
DATA_IN13
DATA_IN15
DATA_IN11
DATA_IN10
DATA_IN7
DATA_IN6
DATA_IN2
DATA_IN5
DATA_IN3
DATA_IN4
GND
DATA_IN0
DATA_IN1
GND
1
3 2
J5
BNC
GND
1
TP4
1 TP2 1 TP3
1 TP1
1
TP5
C86
1u
S1
B3S-1002
RESET_TRSTb
R21
2K2
GND
PCLK
C59
100N
GND
1
3 2
J3
SMA
GND
DATA_IN[19..0]
R18 2K2
R20 2K2
R16 2K2 DVB_ASI
SD/HDb
SMPTE_BY PASSb
FEMALE
DATA_IN19
Install VERTICAL for DVB/ASI
GND
J6
Install HORIZONTAL for SMPTE
DATA_IN18
+3.3V
+3.3V
+1.8V
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
JP1
SQT-105-01-F-D-RA
GND
SDOUT_TDO
SDIN_TDI
+3.3V
RESET_TRSTb
2
4
6
8
10
1
3
5
7
9
JP12
HEADER 5X2
CSb_TMS
Vref _IO
GND
IO_VDD
GND
1
2
C45
1U
+3.3V_CD
1
2
C46
1U
R26 0R
C47
10N C44
10N