GS1572
A Gui
d
e to D
e
sign
ing
with
t
h
e GS157
2
(EB
1572)
Reference Design
46282 - 1
N
ov
emb
e
r 2009
12 o
f 18
Prop
ri
eta
ry
& Co
nfide
n
tial
Figure
4
-2
: Chip Level
D
V
B_ASI
GN
D
_
A
C8
3
10nF
SD
/H
D
b
20bit
/10bit
b
IO
P
R
O
C
_
E
N/DIS
b
H
V
F
GN
D
SM
PT
E_BY
PASSb
GN
D
_
A
GN
D
DE
T
E
CT
_
T
RS
S
D
O
U
T_
TD
O
GN
D
C8
7
10nF
GN
D
ST
AN
D
B
Y
_
IN
V
VI
N
3
OU
T
1
EN
4
GND
5
GND
2
U1
7
M
IC
94060
C6
5
10n
CABLE DRIVER POWER DOWN SWITCH (IN STANDBY MODE)
C
D
_VD
D
_SW
IT
C
H
E
D
GN
D
_
A
C
P_R
ES
B7
VC
O_VC
C
A8
VC
O_GN
D
B8
CORE
_G
ND
E7
VC
O
A9
TI
M_
8
6
1
G3
PC
LK
B4
IO_
VDD
G1
DIN1
8
A2
DIN1
9
B3
LF
A7
CP_
VDD
A10
CP_
GND
B10
DIN1
7
A1
CORE
_V
DD
K8
RS
V
H6
DE
T
E
CT
_
T
RS
F3
CORE
_G
ND
E6
VC
O_GN
D
B9
DIN1
6
B2
CORE
_V
DD
G10
PD_VD
D
A6
PD_VD
D
B6
CORE
_G
ND
D5
ST
AN
D
B
Y
D3
RS
V
K7
RS
V
J7
RS
V
J6
DIN1
4
C2
DIN1
5
B1
CORE
_G
ND
C5
CORE
_G
ND
B5
NC
D6
NC
D7
D
V
B_ASI
G5
LOC
KED
H4
RS
V
H5
RS
V
K6
DIN1
2
C3
DIN1
3
C1
NC
D8
NC
E8
NC
F8
SD
/H
D
E3
CORE
_G
ND
E5
CORE
_V
DD
E1
RS
V
K5
IO_
VDD
H10
DIN1
0
D2
DIN1
1
D1
CORE
_G
ND
F4
CORE
_G
ND
J8
CORE
_G
ND
G9
20BI
T
/10BI
T
G4
CORE
_G
ND
F5
CORE
_V
DD
A5
RS
V
J5
IO_
GND
G2
DIN8
F2
DIN9
F1
CORE
_G
ND
F7
CD_G
ND
F9
CD_G
ND
E9
IO
PR
OC
_EN
/D
IS
G7
SM
PT
E_BY
PASS
G6
RE
S
E
T
G8
RS
V
J4
AN
C
_
BLAN
K
H3
DIN6
H2
DIN7
H1
CD_G
ND
D9
CORE
_G
ND
E2
RS
V
H7
CS
_
T
M
S
K9
SC
LK_T
C
K
J1
0
SD
OU
T
_
T
D
O
J9
RS
V
K4
H/HS
Y
N
C
A4
DIN4
J2
DIN5
J1
CORE
_G
ND
F6
PD_GN
D
C8
PD_GN
D
C7
PD_GN
D
C6
S
D
O
_
E
N
/DIS
D4
SD
IN
_T
D
I
K10
V/
VSY
N
C
C4
IO_
GND
H9
DIN2
K2
DIN3
K1
R
SET
F1
0
CD
_VDD
E10
SD
O
C1
0
SD
O
D1
0
CD_G
ND
C9
JT
A
G
/HO
S
T
H8
F/DE
A3
NC
E4
DIN0
K3
DIN1
J3
U1
8
GS1572
C8
4
10nF
+3
.3
V
T
IM
_861
GN
D
_
A
D
V
B_ASI
JT
A
G
/HO
S
T
b
H
VC
O_GN
D
C8
2
10nF
C8
1
10nF
+1
.8
V
+1
.8
V
DA
T
A
_
IN1
4
C6
7
4u7
CD_V
DD_
SW
ITCHED
PC
LK
SC
LK_T
C
K
R5
8
10K
SD
IN
_T
D
I
DA
T
A
_
IN1
5
R
6
5
75R
L2
5N
6
R
6
0
75R
L1
5n6
1
2
C
7
5
4u7
+1
.8
V
1
2
C
7
2
4u7
R6
6
22k
SD
O-
SD
O+
R and L form the Output Return
Loss compensation Network.
SUBJECT TO CHANGE
DA
T
A
_
IN1
6
VC
O_GN
D
R6
2
75R
JT
A
G
/HO
S
T
b
C7
3
10nF
DE
T
E
CT
_
T
RS
R
6
4
75R
DA
T
A
_
IN1
7
AN
C
_
BLAN
Kb
20bit
/10bit
b
1
2
C
6
3
4u7
1
2
C6
8
0
.2
5
p
C
7
0
10nF
C6
2
0.
25p
OPTIONAL TERMINATIONS
R5
5
0R
R5
4
0R
DA
T
A
_
IN1
8
SD
On
SD
O
GN
D
DA
T
A
_
IN1
9
C6
6
10n
R6
9
(N
P)
C7
8
(N
P)
R6
8
(N
P)
GN
D
C7
7
(N
P)
R6
7
(N
P)
C7
6
(N
P)
VC
O_VC
C
1
2
C7
1
10u
VC
O_GN
D
PLACE CLOSE TO GS1572.
ISOLATE WITH A MOAT ON
ALL LAYERS.
GN
D
R5
6
3R
3
DA
T
A
_
IN0
R5
7
7R
LOC
KED
DA
T
A
_
IN1
DA
T
A
_
IN2
DA
T
A
_
IN3
ST
AN
D
B
Y
SD
O_EN
/D
IS
b
PLACE AS CLOSE AS
POSSIBLE TO THE PINS
OF THE GS1572.
IO
_
V
DD
DA
T
A
_
IN4
DA
T
A
_
IN5
VC
O_GN
D
IO
PR
OC
_EN
/D
ISb
DA
T
A
_
IN6
SM
PT
E_BY
PASSb
SD
/H
D
b
DA
T
A
_
IN7
+3
.3
V
_
C
D
IO
_
V
DD
DA
T
A
_
IN[1
9
..0
]
J8
GN
D
D
A
T
A
_I
N
[19:
0]
R
E
SET
_
T
R
ST
b
DA
T
A
_
IN8
CORE_VDD, IO_VDD DECOUPLING
DA
T
A
_
IN9
D
V
B_ASI
SD
/H
D
b
DA
T
A
_
IN1
0
SM
PT
E_BY
PASSb
DA
T
A
_
IN1
1
IO
_
V
DD
2.5V INTERNAL ISOLATED POWER
VC
O_VC
C
J9
GN
D
IO
_
V
DD
C8
8
10nF
VC
T
R
5
GND
4
GND
8
GN
D
2
VC
C
7
O/
P
1
NC
3
GN
D
6
U1
5
GO1555
C6
4
NP
1
2
C6
9
33u
VC
O_GN
D
+
3
.3V_C
D
R6
1
750R
0
DA
T
A
_
IN1
2
DA
T
A
_
IN1
3
GN
D
IO
_
V
DD
J1
0
GN
D
RE
S
E
T
_
T
RS
T
b
V
IO
_
V
DD
VC
O_GN
D
IO
_
V
DD
GN
D
IO
_
V
DD
J1
2
GN
D
IO
_
V
DD
J1
3
GN
D
J1
4
GN
D
IO
_
V
DD
J1
1
TI
M_
8
6
1
ST
AN
D
B
Y
IO
_
V
DD
J1
6
GN
D
IO
_
V
DD
IO
_
V
DD
GN
D
IO
_
V
DD
CS
b
_
T
M
S
J1
7
GN
D
J1
5
VC
O_GN
D
+3
.3
V
_
C
D
SD
O_EN
/D
IS
b
VC
O_GN
D
AN
C
_
BLAN
Kb
NOTE: VCO_VCC and VCO_GND are the outputs from an
internal voltage regulator. They supply power to
the GO1555 External VCO.
LOC
K
ED
S
T
A
NDB
Y
_
INV
R7
1
1K
1A
1
1Y
2
2A
3
2Y
4
3A
5
3Y
6
GND
7
4Y
8
4A
9
5Y
10
5A
11
6Y
12
6A
13
VCC
14
U2
2
74LVC
04/
SO
+3
.3
V
+3
.3
V
IO
_
V
DD
C8
9
10nF
GN
D
GN
D
R5
500R
2
1
D1
LED
ST
AN
D
B
Y
J7
SD
IN
_T
D
I
SC
LK_T
C
K
C
S
b_T
M
S
SD
OU
T
_
T
D
O
C7
9
10nF
PC
LK
F
C8
0
10nF
