GENNUM EB1572, Reference Design

Page: 5 / 18

GS1572 A Guide to Designing with the GS1572
(EB1572)
Reference Design
46282 - 1
November 2009
5 of 18
Proprietary & Confidential
Figure 2-1: Power Supply Isolation Method
2.2 Serial Digital Outputs
The serial digital differential outputs are designed to be SMPTE compliant for voltage
level, rise/fall time and return loss specifications.
Figure 2-2 shows the recommended
SDO layout and component placement. Ground and power plane voids are placed
under the ORL matching network. The cutouts under the pull-up resistors attached to
the output pins are necessary and are used to reduce the capacitance and provide better
matching to the 75
Ω
transmission line.
Additional points relating to SDO layout and component placement ( Figure 2-2 ):
1. Place the pull-up resistors close to the SDO and SDO pins of the GS1572.
2. Try to avoid running high speed traces through vias.
.
Figure 2-2: Recommended Layout of SDO Section of PCB
ISOLATED
PLANE
+
VIA TO GROUND
VIA TO POWER
GROUND PLANE
POWER PLANE
FB
FB
+
POWER PLANE
GROUND PLANE
VIA TO POWER
VIA TO GROUND
MAIN PLANE
Plane Layer,
Negative Image
Power and Ground
Plane Voids