GENNUM EB-GS2972, User Manual

Page: 7 / 22

EB-GS2972
Evaluation Board User Guide
50283 - 2
May 2012
7 of 22
1.3 Inputs
1.3.1 Audio Input
Up to 8 channels of audio are supported by the EB-GS2972.
Group One (AES 1/J13 and AES 2/J14) goes to SRCs. Through the software, the SRC can
be programmed to output AES or serial (synchronous or asynchronous) audio signals to
the GS2972. The master clock for the SRCs is supplied by the GS4911B on the
EB-GS2972.
Group Two can be connected directly to the GS2972 as AES (AES 3/J15 and AES 4/J16)
or serial audio (Header J30). In the case where synchronous audio is required, external
synchronization must be applied. This configuration is meant to allow users to have the
capability of evaluating audio embedding. For SD audio, when embedding audio with
both groups, the audio needs to be synchronized externally.
1.3.2 Parallel Video Input
The EB-GS2972 has a 48-pin parallel connector for the serialized video input (J25). The
video input includes the 20-bit video data and pixel clock.
The related timing signals (F,V,H) are on the 10-bit parallel connector (J27).
1.4 SDI Outputs (J3 and J4)
The EB-GS2972 includes two SDI outputs on J3 and J4.
ANC_BLANKn
( S W7)
Connected to the G S 2972 ANC_BLANK pin.
When ANC_BLANK is LOW, the Luma and Chroma input data is set to the appropriate b lanking levels during the
H and V b lanking intervals.
When ANC_BLANK is HIGH, the Luma and Chroma data pass through the device unaltered. Only applica b le in
S MPTE mode.
GRP1_EN/DI S n
( S W7)
Connected to the G S 2972 GRP1_EN/DI S pin. Ena b le Input for Audio Group 1. S et HIGH to ena b le.
GRP2_EN/DI S n
( S W7)
Connected to the G S 2972 GRP2_EN/DI S pin. Ena b le Input for Audio Group 2. S et HIGH to ena b le.
S TANDBY
( S W7)
Connected to the G S 2972 S TANDBY pin. HIGH to power-down device.
NOTE: Ca b le Driver is not powered down.
JTAG_HO S Tn
( S W7)
Connected to the G S 2972 JTAG/HO S T pin. Used to select JTAG test mode or Host Interface mode.
When JTAG/HO S T is HIGH, the Host Interface port is configured for JTAG test.
When JTAG/HO S T is LOW, normal operation of the Host Interface port resumes and the separate JTAG pins
b ecome the JTAG port (JP1).
Table 1-1: SW6 and SW7 Settings
Bit Name Description