PACE Series SCPI Manual
K0472 Revision A
3 - 7
3.4
Status Byte group
The status byte group are 8 bit registers that are read by the IEEE 488 standard commands.
The event register is cleared by reading it; the event and enable registers are cleared by the
*CLS command.
Bits within the status byte are a summary of other data structures in the status system.
These bits will become set if other parts of the status system indicates that they should do so
(i.e., a message in the output queue or error queue or, a condition and enable set in a register
pair).
If the associated bit in the status enable register is set, a serial poll is generated and bit 6 is
set. The enable register may be set through the *SRE command so that only selected status
bits cause a serial poll.
Note:
Bit 6 of the enable register is always set to 0.
There are some small differences between * STB? and serial polling. Either method can be
used to read the state of bits 0-5 and bit 7. The reading method is different for bit 6 when
using *STB? and serial poll. In general, use serial polling inside interrupt service routines, not
*STB?
Bit 2 - EAV sets when there is an error in the error queue. The :SYST:ERR? command has to be sent
to retrieve the error. The error queue buffers a maximum of five errors. When no more
errors are available the message “No Error” is returned.
Bit 4 - MAV sets when there is a message available in the output queue.
logical
OR
*STB?
*SRE?
Event
Enable
SERIAL POLL
ESB
MSS
OSB
MAV
QUE
ESB
OSB
MAV
QUE
Standard event
Standard
operation
Output queue
Question data
EAV
EAV
Error queue
MSS
