GE MiCOM P40 Agile, Technical Manual, Page: 876 / 962

Appendix B -Settings and Signals P446SV
B130 P446SV-TM-EN-1
MENU TEXT COL ROW DEFAULT SETTING AVAILABLE OPTIONS
DESCRIPTION
[Indexed String]
When Enabled, CB Fail timers will be reset by drop off of a weak infeed trip condition, providing that WI trip logic is activated.
UNDER CURRENT
45 0A
I< Current Set 45 0B 0.05
From 0.02*I1 to 3.2*I1 in steps of 0.01*I1
[Courier Number (current)]
Setting that determines the circuit breaker fail timer reset current for overcurrent based protection circuit breaker fail initiation. This setting
is also used in the pole dead logic to determine the status of the pole (dead or live).
ISEF< Current 45 0D 0.02
From 0.001*I3 to 0.8*I3 in steps of 0.0005*I3
[Courier Number (current)]
Setting that determines the circuit breaker fail timer reset current for Sensitive earth fault (SEF) protection circuit breaker fail initiation.
PoleDead Voltage
45 0E
V< 45 10 38.1
From 10*V1 to 40*V1 in steps of 0.1*V1
[Courier Number (voltage)]
Under voltage level detector for pole dead detection
GROUP 1: SUPERVISION
46 00
This column contains settings for Voltage and Current Supervision
VTS Mode 46 01 Me MCB
Me MCB
Measured Only
MCB Only
[Indexed String]
Setting that determines the method to be used to declare VT failure.
VTS Status 46 02 Blocking
Disabled
Blocking
Indication
[Indexed String]
This setting determines whether the following operations will occur upon detection of VTS.
• VTS set to provide alarm indication only.
• Optional blocking of voltage dependent protection elements.
• Optional conversion of directional overcurrent elements to non-directional protection
(available when set to blocking mode only). These settings are found in the function links cell of the relevant protection element columns in
the menu.
VTS Reset Mode 46 03 Auto
Manual
Auto
[Indexed String]
The VTS block will be latched after a user settable time delay ‘VTS Time Delay’. Once the signal has latched then two methods of resetting
are available. The first is manually via the front panel interface (or remote communications) and secondly, when in ‘Auto’ mode, provided the
VTS condition has been removed and the 3 phase voltages have been restored above the phase level detector settings for more than 240 ms.
VTS Time Delay 46 04 5
From 1 to 10 in steps of 0.1
[Courier Number (time-seconds)]
Setting that determines the operating time-delay of the element upon detection of a voltage supervision condition.
VTS I> Inhibit 46 05 10
From 0.08*I1 to 32*I1 in steps of 0.01*I1
[Courier Number (current)]
The setting is used to override a voltage supervision block in the event of a phase fault occurring on the system that could trigger the
voltage supervision logic.
VTS I2> Inhibit 46 06 0.05
From 0.05*I1 to 0.5*I1 in steps of 0.01*I1
[Courier Number (current)]
The setting is used to override a voltage supervision block in the event of a fault occurring on the system with negative sequence current
above this setting which could trigger the voltage supervision logic.
Inrush Detection 46 0E Disabled
Disabled
Enabled
[Indexed String]
This setting is to enable/disable the Inrush Detection used for the Distance protection.
I>2nd Harmonic 46 0F 20
From 10 to 100 in steps of 5
[Courier Number (percentage)]
If the level of second harmonic in any phase current or neutral current exceeds the setting, inrush conditions will be recognized by changing
the status of four DDB signals from low to high in the Programmable Scheme Logic (PSL). The user then has a choice to use them further in
the PSL in accordance with the application.
WI Inhibit
46 11 Enabled Disabled