GSP665x-EVBIMS2
High Power IMS 2 Evaluation Platform
Technical Manual
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GSP665x-EVBIMS2 TM rev. 201021
© 2020 GaN Systems Inc.
Please refer to the Evaluation Board/Kit Important Notice on page 22
1.4.4
External PWM Signals Input
Figure 9 External PWM signals connector
The PWM signals of all four GaN devices come from the external PWM connector J1, as shown in Figure 9.
The deadtime of PWM signals are required and should be provided from the external source.
1.4.5
Installation of IMS 2 Half Bridge Power Board
To achieve the lowest power loop parasitics, it is suggested to solder the IMS 2 half bridge power board to
the IMS 2 EVB motherboard.
1.4.6
DC link decoupling capacitors
As it is challenging to create low inductance power loop on single-layer IMS board, DC decoupling
capacitors are placed on multi-layer IMS 2 EVB PCB. The power loop path is highlighted as below.
Figure 10 - Cross section view of IMS assembly showing the power Loop path
