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Fujitsu MHN2100AT - Mobile 10 GB Hard Drive Product Manual Download Page 37

2.2 System Configuration

C141-E120-02EN

2-5

IMPORTANT

HA (host adaptor) consists of address decoder, driver, and receiver.
ATA is an abbreviation of “AT attachment”. The disk drive is
conformed to the ATA-5 interface.

At high speed data transfer (PIO mode 4 or DMA mode 2 U-DMA
mode 5), occurrence of ringing or crosstalk of the signal lines (AT
bus) between the HA and the disk drive may be a great cause of the
obstruction of system reliability. Thus, it is necessary that the
capacitance of the signal lines including the HA and cable does not
exceed the ATA-5 standard, and the cable length between the HA
and the disk drive should be as short as possible.

No need to push the top cover of the disk drive. If the over-power
worked, the cover could be contacted with the spindle motor. Thus,
that could be made it the cause of failure.

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Summary of Contents for MHN2100AT - Mobile 10 GB Hard Drive

Page 1: ...C141 E120 02EN MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...y for incidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal...

Page 3: ...ition and specification were corrected 1 10 Load Unload Function Soft Reset was deleted 3 1 page Account was added 3 1 Dimension Tolerance was corrected 6 Handling caution 3 2 Recommended equipment were changed Table 5 3 Command was added CHAPTER 5 Interface Changed and added 02 2001 09 03 CHAPTER 6 Operation Changed and added 1 Section s with asterisk refer to the previous edition when those were...

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Page 5: ...his chapter gives an overview of the MHN Series and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the MHN Series and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the MHN Series CHAPTER 4 Theory of D...

Page 6: ... signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the ...

Page 7: ...nvolve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 9: ...rform the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handl...

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Page 11: ...ES PRODUCT MANUAL C141 E120 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES MAINTENANCE MANUAL C141 E120 Maintenance and Diagnosis Removal and Replacement Procedure ...

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Page 13: ... 2 2 Model and product number 1 5 1 3 Power Requirements 1 5 1 4 Environmental Specifications 1 7 1 5 Acoustic Noise 1 8 1 6 Shock and Vibration 1 8 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 1 10 Load Unload Function 1 10 CHAPTER 2 Device Configuration 2 1 2 1 Device Configuration 2 2 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2 dri...

Page 14: ...default setting 3 12 3 4 3 Master drive slave drive setting 3 12 3 4 4 CSEL setting 3 13 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Head 4 2 4 2 3 Spindle 4 3 4 2 4 Actuator 4 3 4 2 5 Air filter 4 3 4 3 Circuit Configuration 4 4 4 4 Power on Sequence 4 7 4 5 Self calibration 4 8 4 5 1 Self calibration contents 4 8 4 5 2 Execution timing of s...

Page 15: ...5 3 5 2 Logical Interface 5 6 5 2 1 I O registers 5 7 5 2 2 Command block registers 5 8 5 2 3 Control block registers 5 13 5 3 Host Commands 5 13 5 3 1 Command code and parameters 5 14 5 3 2 Command descriptions 5 16 5 3 3 Error posting 5 88 5 4 Command Protocol 5 90 5 4 1 PIO Data transferring commands from device to host 5 90 5 4 2 PIO Data transferring commands from host to device 5 92 5 4 3 Co...

Page 16: ...5 113 5 6 3 1 Initiating an Ultra DMA data in burst 5 113 5 6 3 2 Ultra DMA data burst timing requirements 5 114 5 6 3 3 Sustained Ultra DMA data in burst 5 117 5 6 3 4 Host pausing an Ultra DMA data in burst 5 118 5 6 3 5 Device terminating an Ultra DMA data in burst 5 119 5 6 3 6 Host terminating an Ultra DMA data in burst 5 120 5 6 3 7 Initiating an Ultra DMA data out burst 5 121 5 6 3 8 Sustai...

Page 17: ... 6 3 2 Alternating defective sectors 6 9 6 4 Read Ahead Cache 6 11 6 4 1 Data buffer configuration 6 12 6 4 2 Caching operation 6 12 6 4 3 Usage of read segment 6 14 6 4 3 1 Mis hit no hit 6 14 6 4 3 2 Sequential read 6 15 6 4 3 3 Full hit hit all 6 18 6 4 3 4 Partially hit 6 19 6 5 Write Cache 6 20 Glossary GL 1 Acronyms and Abbreviations AB 1 ...

Page 18: ...9 Cable connections 3 10 Figure 3 10 Power supply connector pins CN1 3 11 Figure 3 11 Jumper location 3 11 Figure 3 12 Factory default setting 3 12 Figure 3 13 Jumper setting of master or slave drive 3 12 Figure 3 14 CSEL setting 3 13 Figure 3 15 Example 1 of Cable Select 3 13 Figure 3 16 Example 2 of Cable Select 3 14 Figure 4 1 Head structure 4 3 Figure 4 2 Power Supply Configuration 4 5 Figure ...

Page 19: ...ra DMA data out burst 5 121 Figure 5 17 Sustained Ultra DMA data out burst 5 122 Figure 5 18 Device pausing an Ultra DMA data out burst 5 123 Figure 5 19 Host terminating an Ultra DMA data out burst 5 124 Figure 5 20 Device terminating an Ultra DMA data out burst 5 125 Figure 5 21 Power on Reset Timing 5 126 Figure 6 1 Response to power on 6 3 Figure 6 2 Response to hardware reset 6 4 Figure 6 3 R...

Page 20: ...5 9 Format of insurance failure threshold value data 5 69 Table 5 10 Log Directory Data Format 5 73 Table 5 11 SMART error log data format 5 74 Table 5 12 SMART self test log data format 5 76 Table 5 13 Contents of security password 5 77 Table 5 14 Contents of SECURITY SET PASSWORD data 5 81 Table 5 15 Relationship between combination of Identifier and Security level and operation of the lock func...

Page 21: ...ock and Vibration 1 7 Reliability 1 8 Error Rate 1 9 Media Defects 1 10 Load Unload Function Overview and features are described in this chapter and specifications and power requirement are described The MHN Series are 2 5 inch hard disk drives with built in disk controllers These disk drives use the AT bus hard disk interface protocol and are compact and reliable ...

Page 22: ...e disk drive supports an external data rate up to 100 MB s U DMA mode 5 4 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms at read 1 1 2 Adaptability 1 Power save mode The power save mode feature for idle operation stand by and sleep modes makes The disk drives the MHN Series id...

Page 23: ...e another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Master slave The disk drives the MHN Series can be connected to ATA interface as daisy chain configuration Drive 0 is a master device drive 1 is a slave device 5 Error correction and retry by ECC If a recoverable error occurs the disk drive...

Page 24: ...2 Recording Method 16 17 MTR Track Density 1 98 K track mm 50 400 TPI Bit Density 22 75 K bit mm 578 0 KBPI Rotational Speed 4 200 rpm 1 Average Latency 7 14 ms Positioning time read and seek Minimum Track to Track Average Maximum Full 1 5 ms typ Read 12 ms typ 22 ms typ Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typ 5 sec Typ 5 sec Interface ATA 5 Max Cable length 0 46 m Data Tr...

Page 25: ... MHN2150AT 8 45 GB 16 383 16 63 MHN2100AT 8 45 GB 16 383 16 63 1 2 2 Model and product number Table 1 2 lists the model names and product numbers of the MHN Series Table 1 2 Model names and product numbers Model Name Capacity user area Mounting screw Order No MHN2300AT 30 GB M3 depth 3 CA05456 B041 MHN2200AT 20 GB M3 depth 3 CA05456 B131 MHN2150AT 15 GB M3 depth 3 CA05456 B021 MHN2100AT 10 GB M3 d...

Page 26: ... 0 1 W Energy Efficiency 4 0 025 W GB rank E MHN2300AT 0 025 W GB rank E MHN2200AT 0 050 W GB rank D MHN2150AT 0 050 W GB rank D MHN2100AT 1 Current at starting spindle motor 2 At 30 disk accessing 3 Power requirements reflect nominal values for 5V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing power consumption by the stor...

Page 27: ... concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 9...

Page 28: ...1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 400 Hz 9 8m s2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 1715 m s2 0 peak 175G 0 peak 2ms duration without non recovered ...

Page 29: ...R The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operat...

Page 30: ... error Positioning seek errors that can be recovered by one retry shall occur no more than 10 times in 107 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk the MHN Series are formatted prior to shipment from the factory low level format Thus the hosts see a defect free devices Alternate sectors are automatically accessed by the disk drive The user need...

Page 31: ...d when the power is shut down while the heads are still loaded on the disk The product supports the Emergency Unload a minimum of 20 000 times When the power is shut down the controlled Normal Unload cannot be executed Therefore the number of Emergency other than Normal Unload is specified ...

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Page 33: ... 1 CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 34: ...sk is 65 mm The inner diameter is 20 mm The number of disks used varies with the model as described below MHN2300AT 2 disks MHM2200AT 2 disks MHM2150AT 1 disk MHM2100AT 1 disk 2 Head The heads are of the load unload L UL type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts Figure 2 2 illustrates the configuration of the disks and heads of ...

Page 35: ...tor is stopped the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk This system continuously circulates the air through the circulation filter to mainta...

Page 36: ...de 5 transfer at 100 MB s 2 2 2 1 drive connection MHC2032AT MHC2040AT Figure 2 3 1 drive system configuration 2 2 3 2 drives connection MHC2032AT MHC2040AT MHC2032AT MHC2040AT Host adaptor Note When the drive that is not conformed to ATA is connected to the disk drive above configuration the operation is not guaranteed Figure 2 4 2 drives configuration MHG2102AT MHH2064AT MHH2032AT MHN2300AT MHN2...

Page 37: ...lk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 5 standard and the cable length between the HA and the disk drive should be as short as possible No need to push the top cover of the disk drive If the over powe...

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Page 39: ...er Settings This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives For information about handling this hard disk drive and the system installation procedure refer to the following Integration Guide C141 E144 ...

Page 40: ...tallation Conditions 3 2 C141 E120 02EN 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm 0 25 Figure 3 1 Dimensions ...

Page 41: ... 3 3 3 2 Mounting 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive a Horizontal 1 b Horizontal 1 c Vertical 1 d Vertical 2 e Vertical 3 f Vertical 4 Figure 3 2 Orientation gravity gravity gravity ...

Page 42: ...5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Figure 3 3 Mounting frame structure Screw Screw Details of B Details of A 3 0 or less 3 0 or less Frame of system cabinet Fr...

Page 43: ...Because of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around φ3 to block Figure 3 4 Location of breather ...

Page 44: ...ace temperature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperat...

Page 45: ...not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cautions and handle th...

Page 46: ...rque of the screw strictly M3 0 49 N m 5 Kg cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid fa...

Page 47: ... Connections 3 3 1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals Figure 3 8 Connector locations Connector setting pins PCA ...

Page 48: ...ply cable 44 pin type Cable socket 44 pin type 89361 144 BERG IMPORTANT For the host interface cable use a ribbon cable A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines This is because the interface is designed for ribbon cables and not for cables carrying differential signals 3 3 3 Device connection Figure 3 9 shows how to c...

Page 49: ... 3 10 shows the pin assignment of the power supply connector CN1 Figure 3 10 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 11 shows the location of the jumpers to select drive configuration and functions Figure 3 11 Jumper location ...

Page 50: ...n at the factory Figure 3 12 Factory default setting 3 4 3 Master drive slave drive setting Master drive disk drive 0 or slave drive disk drive 1 is selected b Slave drive a Master drive Open Open Short Open A 1 C B D 2 B D 2 A C 1 Figure 3 13 Jumper setting of master or slave drive Note Pins A and C should be open Open ...

Page 51: ...ion using unique interface cables By connecting the CSEL of the master drive to the CSEL Line conducer of the cable and connecting it to ground further the CSEL is set to low level The drive is identified as a master drive At this time the CSEL of the slave drive does not have a conductor Thus since the slave drive is not connected to the CSEL conductor the CSEL is set to high level The drive is i...

Page 52: ...Installation Conditions 3 14 C141 E120 02EN Figure 3 16 Example 2 of Cable Select drive drive ...

Page 53: ...4 3 Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 54: ...dle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm The MHN2300AT and MHN2200AT have two disks and MHN2150AT and MHM2100AT have one disk Servo data is recor...

Page 55: ...rriage along the inner or outer edge of the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessa...

Page 56: ...16 17 MTR Maximum Transitions Limited encoder Run Length and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice c...

Page 57: ...4 3 Circuit Configuration C141 E120 02EN 4 5 Figure 4 2 Power Supply Configuration 5 0V 3 3V 3 0V S DRAM SVC HDIC F ROM MCU HDC RDC 2 5V ...

Page 58: ...Theory of Device Operation 4 6 C141 E120 02EN Figure 4 3 Circuit Configuration ...

Page 59: ...sk drive starts the spindle motor b The disk drive executes self diagnosis data buffer read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The disk drive executes self seek calibration This collects...

Page 60: ...and the cylinder where the head is positioned To execute stable fast seek operations external forces are occasionally sensed The firmware of the drive measures and stores the force value of the actuator motor drive current that balances the torque for stopping head stably This includes the current offset in the power amplifier circuit and DAC system Start Self diagnosis 1 MPU bus test Internal reg...

Page 61: ...d and stored For sensing the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio For compensating the direction current value to the power amplifier is multiplied by the compensation value By this comp...

Page 62: ... 6 1 Read write preamplifier HDIC HDIC equips a read preamplifier and a write current switch that sets the bias current to the MR device and the current in writing Each channel is connected to each data head and HDIC switches channel by serial I O HDIC generates a write unsafe signal WUS when a write error occurs due to head short circuits or head disconnection that avoids error writing 4 6 2 Writ...

Page 63: ...4 6 Read write Circuit C141 E120 02EN 4 11 Table 4 1 Write precompensation algorithm Bits Compensation 111001 111010 111111 000000 000001 010000 100000 7 6 1 0 1 16 32 ...

Page 64: ...k diagram HDIC WDX WDY RDX RDY Write PreCompen sation Serial I O Registers Digital PLL Flash Digitizer MEEPR Viterbi Detect 16 17 ENDEC ServoPulse Detector Programmable Filter AGC Amplifier RDC SD SC SE Position A B C D to reg WTGATE REFCLK RDGATE DATA 7 0 RWCLK SRV_OUT 1 0 SRV_CLK ...

Page 65: ...es The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal C...

Page 66: ...it converts the 17 bit read data into the 16 bit NRZ data 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the reco...

Page 67: ... block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 7 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes the DSP unit and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU Main internal op...

Page 68: ... head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area The logical initial cylinder is at the outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration ...

Page 69: ...verts the VCM drive current value digital value calculated by the DSP unit into analog values and transfers them to the power amplifier 4 Power amplifier The power amplifier feeds currents corresponding to the DAC output signal voltage to the VCM 5 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the...

Page 70: ...ibed below 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving ...

Page 71: ... W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code Erase Servo A Erase Servo A Servo B Erase Servo B Erase Servo C Erase Servo C Erase Servo D Erase PAD CYLn 1 CYLn CYLn 1 n even number Diameter direction Circumference Direction Erase DC erase area OGB Data area IGB expand Servo frame 120 servo frames per revolution ...

Page 72: ...rated from the gray code and servo A to D This servo information is used for positioning operation of radius direction and position detection of circumstance direction The servo frame consists of 6 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 9 shows the servo frame format Figure 4 9 Servo frame format ...

Page 73: ...ded on the data surface The MPU fetches the position sense data on the servo frame at a constant interval of sampling time executes calculation and updates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to posi...

Page 74: ...ference between the target position and the position clarified by the detected position sense data The filtering includes servo compensation These are digitally controlled by the firmware 4 7 5 Spindle motor control Hall less three phase twelve pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC herea...

Page 75: ...rom the SVC and waits till the rotational speed reaches 4 200 rpm When the rotational speed reaches 4 200 rpm the SVC enters the stable rotation mode 3 Stable rotation mode The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal The MPU takes a difference between the current time and a time for one revolution at 4 200 rpm that the MPU already recognized Then the...

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Page 77: ...PTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA Feature Set 5 6 Timing This chapter gives details about the interface and the interface commands and timings ...

Page 78: ... DMA REQUEST INTRO INTERRUPT REQUEST DIOW I O WRITE STOP STOP DURING ULTRA DMA DATA BURSTS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT MSTR Master ENCSEL ENABLE CSEL GND GROUND DIOR I O READ HDMARDY DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE DATA STROBE DURING ULTRA DMA DATA OUT BURST 5V DC 5 volt Host IORDY I O READY DDMARDY DMA READY DURING ULTR...

Page 79: ...11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 MSTR unused KEY RESET DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW STOP DIOR HDMRDY HSTROBE IORDY DDMARDY DSTROBE DMACK INTRQ DA1 DA0 CS0 DASP 5 VDC GND B D F 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 MSTR ENCSEL ENCSEL KEY GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND rese...

Page 80: ... by the host later indicates that the transfer has been suspended DIOR I Read strobe signal from the host to read the device register or data port HDMARDY I Flow control signal for Ultra DMA data In transfer READ DMA command This signal is asserted by the host to inform the device that the host is ready to receive the Ultra DMA data In transfer The host can negate the HDMARDY signal to suspend the...

Page 81: ...nd a slave device is present This signal is pulled up to 5 V through 10 kΩ resistor at each device IORDY O This signal requests the host system to delay the transfer cycle when the device is not ready to respond to a data transfer request from the host system DDMARDY O Flow control signal for Ultra DMA data Out transfer WRITE DMA command This signal is asserted by the device to inform the host tha...

Page 82: ...nal from the host to the device O indicates output signal from the device to the host I O indicates common output or bi directional signal between the host and the device 5 2 Logical Interface The device can operate for command execution in either address specified mode cylinder head sector CHS or Logical block address LBA mode The IDENTIFY DEVICE information indicates whether the device supports ...

Page 83: ...ow Cylinder Low X 1F4 L H H L H Cylinder High Cylinder High X 1F5 L H H H L Device Head Device Head X 1F6 L H H H H Status Command X 1F7 L L X X X Invalid Invalid Control block registers H L H H L Alternate Status Device Control X 3F6 H L H H H X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation ...

Page 84: ... Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICRC UNC X IDNF X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC Error ICRC This bit indicates that a CRC error occurred during Ultra DMA transfer Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectab...

Page 85: ...ead or write operation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from t...

Page 86: ...der 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B...

Page 87: ...tem should not write the command block registers If the host system reads any command block register when BSY bit is 1 the contents of the Status register are posted This bit is set by the device under following conditions a Within 400 ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is...

Page 88: ...tes that the device is ready to transfer data of word unit or byte unit between the host system and the device Bit 2 Always 0 Bit 1 Always 0 Bit 0 Error ERR bit This bit indicates that an error was detected while the previous command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a comman...

Page 89: ...he device is held reset state When two device are daisy chained on the interface setting this bit resets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this b...

Page 90: ...0 R N Y Y Y Y WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D SET FEATURES 1 1 ...

Page 91: ... N D SMART 1 0 1 1 0 0 0 0 Y Y Y Y D SECURITY DISABLE PASSWORD 1 1 1 1 0 1 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 Y N ...

Page 92: ...indication of the I O registers at command completion are shown as following in this subsection Example READ SECTOR S At command issuance I O registers setting contents Bit 7 6 5 4 3 2 1 0 1F7H CM 0 0 1 0 0 0 0 0 1F6H DH x L x DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At ...

Page 93: ...r Number registers Number of sectors can be specified from 1 to 256 sectors To specify 256 sectors reading 00 is specified For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 1 If the head is not on the track specified by the host the device performs an implied seek After the head reaches to the specified track the device reads the target sector If an error occurs retry...

Page 94: ...tors of which data was not transferred is set in this register 2 READ MULTIPLE X C4 The READ MULTIPLE Command performs the same as the READ SECTOR S Command except that when the device is ready to transfer data for a block of sectors and enters the interrupt pending state only before the data transfer for the first sector of the block sectors In the READ MULTIPLE command operation the DRQ bit of t...

Page 95: ... an ABORTED COMMAND error Figure 5 2 shows an example of the execution of the READ MULTIPLE command Block count specified by SET MULTIPLE MODE command 4 number of sectors in a block READ MULTIPLE command specifies Number of requested sectors 9 Sector Count register 9 Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6...

Page 96: ... status as the result of command execution only once at completion of the data transfer When an error such as an unrecoverable medium error that the command execution cannot be continued is detected the data transfer is stopped without transferring data of sectors after the erred sector The device generates an interrupt using the INTRQ signal and posts a status to the host system The format of the...

Page 97: ...s not transferred is set in this register 4 READ VERIFY SECTOR S X 40 or X 41 This command operates similarly to the READ SECTOR S command except that the data is not transferred to the host system After all requested sectors are verified the device clears the BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain ...

Page 98: ...address specified in the Device Head Cylinder High Cylinder Low and Sector Number registers to the address specified in the Sector Count register Number of sectors can be specified from 1 to 256 sectors A sector count of 0 requests 256 sectors Data transfer begins at the sector specified in the Sector Number register For the DRQ INTRQ and BSY protocols related to data transfer see Subsection 5 4 2...

Page 99: ...nts 1F7H CM 0 0 1 1 0 0 0 R 1F6H DH x L x DV StartheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder...

Page 100: ...f sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when WRITE MULTIPLE command is disabled the device rejects the WRITE MULTIPLE command with an ABORTED COMMAND error Disk errors encountered during execution of the WRITE MULTIPLE command are posted after...

Page 101: ... SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a status as the result of command execution only once at completion of the data transfer or completion of processing in the device The device posts a status as the result of command execution only on...

Page 102: ...rmation 1F6H DH x L x DV EndheadNo LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command excep...

Page 103: ...F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the S...

Page 104: ...L 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information Note Also executable in LBA mode 10 SEEK X 7x x X 0 to X F This command performs a seek operation to the track and selects the head specified in the command block registers After completing the seek operation the device clears the BSY bit in the Status register and generates an interrupt In the LBA mode this command performs the seek operatio...

Page 105: ...X 91 The host system can set the number of sectors per track and the maximum head number maximum head number is number of heads minus 1 per cylinder with this command Upon receipt of this command the device sets the BSY bit of Status register and saves the parameters Then the device clears the BSY bit and generates an interrupt When the SC register is specified to X 00 an ABORTED COMMAND error is ...

Page 106: ...C 1F1H ER xx xx xx Number of sectors track Error information 12 IDENTIFY DEVICE X EC The host system issues the IDENTIFY DEVICE command to read parameter information from the device Upon receipt of this command the drive sets the BSY bit to one prepares to transfer the 256 words of device identification data to the host sets the DRQ bit to one clears the BSY bit to zero and generates an interrupt ...

Page 107: ...he same way as the Identify Device command At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 1 1 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 108: ... xx Error information Table 5 4 Information to be read by IDENTIFY DEVICE command 1 of 3 Word Value Description 0 X 045A General Configuration 1 1 2 Number of Logical cylinders 2 2 X C837 Detailed Configuration 3 2 Number of Logical Heads 2 4 5 X 0000 Undefined 6 2 Number of Logical sectors per Logical track 2 7 9 X 0000 Undefined 10 19 Set by a device Serial number ASCII code 20 characters right ...

Page 109: ...ctors per track 57 58 Variable Total number of current sectors 59 6 Transfer sector count currently set by READ WRITE MULTIPLE command 6 60 61 2 Total number of user addressable sectors LBA mode only 2 62 X 0000 Reserved 63 X xx07 Multiword DMA transfer mode 7 64 X 0003 Advance PIO transfer mode support status 8 65 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns 66 X 0078 Manufact...

Page 110: ...4 Variable Acoustic Management level 95 127 X 0000 Reserved 128 Variable Security status 18 129 159 X 0000 Undefined 160 254 X 0000 Reserved 255 X xxA5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units 1 Word 0 General configuration Bit 15 ATA device 0 ATAPI device 1 Bit 14 8 Undefined Bit 7 Removable disk drive 1 Bit ...

Page 111: ...e word 88 Bit 1 1 Enable the word 64 70 Bit 0 1 Enable the word 54 58 6 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bit 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bit 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 7 Word 63 Multiword DMA transfer mode Bit 15 8 Currently used multiw...

Page 112: ...mmand Bit 11 Undefined Bit 10 1 Supports the Host Protected Area feature set Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Supports the SERVICE interrupt Bit 7 1 Supports the release interrupt Bit 6 1 Supports the read cache function Bit 5 1 Supports the write cache function Bit 4 1 Supports the PACKET command feature set Bit 3 1 Supports the power management feature set Bit 2 1 Supports the R...

Page 113: ...anced Power Management feature set Bit 2 1 Supports the CFA Compact Flash Association feature set Bit 1 1 Supports the READ WRITE DMA QUEUED command Bit 0 1 Supports the DOWNLOAD MICROCODE command 12 WORD 84 Bit 15 3 Undefined Bit 2 1 Supports the Media Serial Number Bit 1 1 Supports the SMART SELF TEST Bit 0 1 Supports the SMART Error Logging 13 WORD 85 Bit 15 Undefined Bit 14 1 Enables the NOP c...

Page 114: ...urity extending function Bits 7 6 Same definition as WORD 83 Bit 5 1 Enables the Power Up In Standby function Bit 4 1 Enables the Removable Media Status Notification function Bit 3 1 Enables the Advanced Power Management function Bits 2 0 Same definition as WORD 83 15 WORD 87 Bits 15 3 Reserved Bit 2 1 Enables the Media Serial Number Bit 1 0 Same definition as WORD 84 16 WORD 88 Bit 15 8 Currently...

Page 115: ...method Bit 8 Reserved Bits 7 0 In the case of Device 0 master drive a valid value is set Bit 7 Reserved Bit 6 1 Device 1 is selected Device 0 responds Bit 5 1 Device 0 assertion of DASP was detected Bit 4 1 Device 0 assertion of PDIAG was detected Bit 3 1 Device 0 an error was not detected in the self diagnosis Bit 2 1 Method for deciding the device No of Device 0 00 Reserved 01 Using a jumper 10 ...

Page 116: ...ter for the purpose of changing the device features to be executed Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Features register Then the device clears the BSY bit and generates an interrupt If the value in the Features register is not supported or it is invalid the device posts an ABORTED COMMAND error Table 5 5 lists the availab...

Page 117: ...write cache function X 85 Disables the advanced power management function X AA Enables the read cache function X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands X C2 Disables the Acoustic management function X CC Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is set as follows Write cashe fu...

Page 118: ...he host sets X 03 to the Features register By issuing this command with setting a value to the Sector Count register the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error...

Page 119: ...nd for a specific time The power management level is shifted from Active Idle and Low power Idle to Standby The Mode 3 takes the maximum shifting time in the APM level The APM level setting is preserved by the drive across power on hardware and software resets APM Level Sector Count register Mode 0 Low Power Idle Mode 1 Low Power Idle Mode 2 Standby Mode 3 Standby Reserved C0h FEh 80h BFh 40h 7Fh ...

Page 120: ...he IDD supports 2 4 8 16 and 32 sectors as the block counts Upon receipt of this command the device sets the BSY bit of the Status register and checks the contents of the Sector Count register If the contents of the Sector Count register is valid and is a supported block count the value is stored for all subsequent READ MULTIPLE and WRITE MULTIPLE commands Execution of these commands is then enabl...

Page 121: ...E and WRITE MULTIPLE command operation are disabled as the default mode At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx Sector count block Error information 16 SET MAX F9 SET MAX Features Register Values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET MAX UNLOCK 04h ...

Page 122: ...ound error will result When SC register bit 0 VV Value Volatile is 1 the value set by this command is held even after power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value default value if not set most lately set when VV bit 1 After power on and t...

Page 123: ... command requests a transfer of 1 sector of data from the host and defines the contents of SET MAX password The password is retained by the device until the next power cycle The READ NATIVE MAX ADDRESS command is not executed just before this command The command is the SET MAX ADDRESS command if it is the command just after the READ NATIVE MAX ADDRESS command is executed At command issuance I O re...

Page 124: ...ts the device into SET_MAX_LOCK state After this command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK commands are rejected And the device returns command aborted The device remains in the SET MAX LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command The READ NATIVE MAX ADDRESS command is not executed just before ...

Page 125: ...r of data transferred shall be compared with the stored password If the password compare fails the device returns command aborted and decrements the Unlock counter and remains in the Set Max Lock state On the acceptance of the SET MAX LOCK command the Unlock counter is set to a value of five When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If t...

Page 126: ...LOCK command sets the device to SET_MAX_Frozen state After the device made a transition to the Set Max Freeze Lock state the following SET MAX commands are rejected then the device returns command aborted SET MAX ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK If the Device is in the SET_MAX_UNLOCK state with the SET MAX FREEZE LOCK command then the device returns command aborted The READ...

Page 127: ...2H SC xx xx xx xx xx 1F1H ER Error information 17 READ NATIVE MAX ADDRESS F8 This command posts the maximum address intrinsic to the device which can be set by the SET MAX ADDRESS command Upon receipt of this command the device sets the BSY bit and indicates the maximum address in the DH CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting ...

Page 128: ...e 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own diagnostic status The device 0 clears the BSY bit of the Status register and generates an interrupt The device 1 does not generate an interrupt A diagnostic status of the device 0 is read by the host system When a diagnostic failure of the device 1 is detec...

Page 129: ...with the result of power on diagnostic test At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 0 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx 01H 1 01H Diagnostic code 1 Thi...

Page 130: ...r of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET FEATURES command At command issuance I O registers setting contents 1F7H CM 0 0 1 0 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB 01 xx R Retry At command completion I O registers contents to be read 1F7H ST Status inform...

Page 131: ...LONG Same address issues sequence After READ LONG is issued WRITE LONG can be issued consecutively If above condition is not satisfied the WRITE LONG Data becomes the Uncorrectable error for subsequence READ command At command issuance I O registers setting contents 1F7H CM 0 0 1 1 0 0 1 R 1F6H DH x L x DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB ...

Page 132: ...sets the DRQ bit of Status register clears the BSY bit and generates an interrupt After that the host system can read up to 512 bytes of data from the buffer At command issuance I O registers setting contents 1F7H CM 1 1 1 1 0 1 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x...

Page 133: ...and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be ...

Page 134: ...ndby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdown after completion of the command execution Th...

Page 135: ...bit of the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status info...

Page 136: ...rts the countdown when the device returns to idle mode When the timer value reaches 0 a specified time has padded the device enters standby mode Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F...

Page 137: ...it and generates an interrupt This command does not support the automatic power down sequence At command issuance I O registers setting contents 1F7H CM X 94 or X E0 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Erro...

Page 138: ...e sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The only way to release the device from sleep mode is to execute a software or hardware reset At command issuance I O registers setting contents 1F7H CM X 99 or X E6 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At c...

Page 139: ...lears the BSY bit and generates an interrupt Power save mode Sector Count register During moving to standby mode Standby mode During returning from the standby mode X 00 Idle mode X FF Active mode X FF At command issuance I O registers setting contents 1F7H CM X 98 or X E5 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be ...

Page 140: ...It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is enabled The device collects or updates several items to forecast failures In the following sections the values of items collected or updated by the device ...

Page 141: ...n on When the automatic saving feature is enabled the attribute values are saved before the device enters the power saving mode However if the failure prediction feature is disabled the attribute values are not automatically saved When the device receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save Attribute Values...

Page 142: ... when it has prepared to receive data from the host computer it sets DRQ and clears the BSY bit Next it receives data from the host computer and writes the specified log sector in the SN register SN Log sector 80h 9Fh Host vendor log The host can write any desired data in the host vendor log X D8 SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintain...

Page 143: ...e passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART Read Attribute Values subcommand FR register D0h SMART Save Attribute Values subcommand FR register D3h or SMART Return Status subcommand FR register DAh to save the dev...

Page 144: ...F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following table 5 8 The host can access this data using the SMART Read Attribute Values subcommand FR register D0h The insurance failure threshold value data is 512 byte data the format of this data is shown the following table 5 8 The host can access this data using the SMART Read Att...

Page 145: ...ine data collection execution time sec 16E Reserved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Vendor unique 174 Simple self test execution time min 175 Comprehensive self test execution time min 176 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 9 Format of insurance failure threshold value data Byte Item 00 ...

Page 146: ...ce 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 196 Reallocated Event Count 197 Current Pending Sector Count 198 Off Line Scan Uncorrectable Sector Count 199 Ultra ATA CRC Error Count 200 Wr...

Page 147: ... worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state nearest to a failure so far Raw attribute value Raw attributes data is retained Off line data collection status Bits 0 to 6 Indicates the situation of off line data collection according to the table below Bit 7 If this bit is 1 it indicates that the automatic off line da...

Page 148: ...ethod of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Bit Meaning 0 Indicates that Execute Off Line Immediate is supported 1 Vendor unique 2 Indicates that off line data collection being executed is aborted when a new command is received 3 Indicates that supports off line read scan func...

Page 149: ... Version 02 Number of sectors of Address 01h 03 0B Reserved 0C Number of sectors of Address 06h 0D FF Reserved 100 Number of sector 101 Address 80h Reserved 102 13F Address 81h Address 9Fh 102 and 13F are both the same format as 100 101 140 1FF Reserved SMART error logging If an unrecoverable error is detected during execution of a command received by the device from the host computer the device s...

Page 150: ... is turned on until command reception 0E to 3D Command Data 2 to 5 The format of each type of command data is the same as that of byte 02 to 0D 3E Error data Reserved 3F Error register 40 Sector Count register 41 Sector Number register 42 Cylinder Low register 43 Cylinder High register 44 Error log 1 Error data Device Head register 45 Status register 46 to 58 Vendor unique 59 Status 5A 5B Total po...

Page 151: ...Error data Indicates the I O register values when the error is reported Status Bits 0 to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear status 1 Sleep status 2 Standby status 3 Active status or idle status BSY bit 0 4 Off line data collection being executed 5 to F Reserved SMART Self Test The host comput...

Page 152: ...ied by this value When the self test index exceeds 21 it returns to 01 Self test index Indicates the latest self test log number If the self test has not been executed 00h is displayed 30 SECURITY DISABLE PASSWORD F6h This command invalidates the user password already set and releases the lock function The host transfers the 512 byte data shown in Table 5 13 to the device The device compares the u...

Page 153: ...tents 0 Control word Bit 0 Identifier 0 Compares the user passwords 1 Compares the master passwords Bits 1 to 15 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 1 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1...

Page 154: ...5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 32 SECURITY ERASE UNIT F4h This command erases all user data This command also invalidates the user password and releases the lock function The host transfers the 512 byte data shown in ...

Page 155: ...e Aborted Command error At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 0 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx xx xx At command completion I O register contents 1F7h ST Status information 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 33 SECURITY FREEZE LOCK F5h This command puts the device into FROZEN MODE ...

Page 156: ...ommand error when the device is in LOCKED MODE READ DMA WRITE DMA SECURITY DISABLE PASSWORD READ LONG WRITE LONG SECURITY FREEZE LOCK READ MULTIPLE WRITE MULTIPLE SECURITY SET PASSWORD READ SECTORS WRITE SECTORS SET MAX READ VERIFY SECTORS WRITE VERIFY FLUSH CACHE At command issuance I O register contents 1F7h CM 1 1 1 1 0 1 0 1 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h FR xx xx xx ...

Page 157: ...ssword 32 bytes 17 Master password version number 18 to 255 Reserved Table 5 15 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is saved as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password o...

Page 158: ...specifies the master password When the master password is selected When the security level is LOCKED MODE is high the password is compared with the master password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the security level in LOCKED MODE is set to the highest level the Aborted Command error is always returned When the use...

Page 159: ...n 1F6h DH x x x DV xx 1F5h CH 1F4h CL 1F3h SN 1F2h SC 1F1h ER xx xx xx xx Error information 36 FLUSH CACHE E7 This command is used to order to write every write cache data stored by the device into the medium BSY bit is held at 1 until every data has been written normally or an error has occurred The device performs every error recovery so that the data are read correctly When executing this comma...

Page 160: ...1F1h ER xx xx xx xx Error information 37 DEVICE CONFIGURATION B1 Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register The following table shows these Features register values If this command sets with the reserved value of Features register an aborted error is posted FR values Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CO...

Page 161: ...ata returned from the execution of a DEVICE CONFIGURATION IDENTIFY command After execution of this command the settings are kept for the device power down or reset If a Host Protected Area has been set by a SET MAX ADDRESS command or if DEVICE CONFIGURATION FREEZE LOCK is set an aborted error is posted DEVICE CONFIGURATION FREEZE LOCK FR C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents ac...

Page 162: ...IGURATION IDENTIFY command The format of the overlay transmitted by the device is described in Table 5 16 The DEVICE CONFIGURATION SET command transfers an overlay that modifies some of the bits set in words 63 82 83 84 and 88 of the IDENTIFY DEVICE command response When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in t...

Page 163: ...e supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 X 00CF Command set feature set supported Bit 15 9 Reserved Bit 8 1 48 bit Addressing feature set supported Bit 7 1 Host Protected Area feature set supported Bit 6 1 Automatic acoustic management supported Bit 5 1 READ WRITE DMA QUEUED commands supported Bit 4 1 Power up in S...

Page 164: ...MA V V V V V V V WRITE DMA V V V V V V WRITE VERIFY V V V V V V READ VERIFY SECTOR S V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V SET MAX ADDRESS V V V V V READ NATIVE MAX ADDRESS V V V V EXECUTE DEVICE DIAGNOSTIC V READ LONG V V V V V WRITE LONG V V V V V REA...

Page 165: ...DY DWF ERR SLEEP V V V V CHECK POWER MODE V V V V SMART V V V V V SECURITY DISABLE PASSWORD V V V V SECURITY ERASE PREPARE V V V V SECURITY ERASE UNIT V V V V SECURITY FREEZE LOCK V V V V SECURITY SET PASSWORD V V V V SECURITY UNLOCK V V V V FLUSH CACHE V V V V V DEVICE CONFIGURATION V V V V Invalid command V V V V V Valid on this command See the command descriptions ...

Page 166: ...EAD LONG command 516 bytes are transferred Following shows the protocol outline a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector of data is available for transfer to the ...

Page 167: ...g Figure 5 3 shows an example of READ SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Figure 5 3 Read Sector s command protocol IMPORTANT For transfer of a sector of data the host needs to read Status register X 1F7 in order to clear INTRQ interrupt signal The Status register should be read within a period from the DRQ setting by the ...

Page 168: ...r operation is not guaranteed When the host new command even if the device requests the data transfer setting in DRQ bit the correct device operation is not guaranteed Figure 5 4 Protocol for command abort 5 4 2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive WRITE SECTOR S WRITE LONG WRITE BUFFER WRITE VE...

Page 169: ...hen the device is ready to receive the data of the first sector the device sets DRQ bit and clears BSY bit d The host writes one sector of data through the Data register e The device clears the DRQ bit and sets the BSY bit f When the drive completes transferring the data of the sector the device clears BSY bit and asserts INTRQ signal If transfer of another sector is requested the drive sets the D...

Page 170: ... does not need to read the Status register for the first and the last sector to be transferred If the timing to read the Status register does not meet above condition normal data transfer operation is not assured guaranteed When the host issues the command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed ...

Page 171: ... IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS SECURITY ERASE PREPARE SECURITY FREEZE LOCK FLUSH CACHE Figure 5 6 shows the protocol for the command execution without data transfer Figure 5 6 Protocol for the command execution without data transfer ...

Page 172: ... WRITE DMA Starting the DMA transfer command is the same as the READ SECTOR S or WRITE SECTOR S command except the point that the host initializes the DMA channel preceding the command issuance Interruption processing for DMA transfer does not issue interruptions in any intermediate sector when a multisector command is executed The following outlines the protocol ...

Page 173: ...e DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data transfer The device asserts either the BSY bit or DRQ bit during DMA data transfer f When the command execution is completed the device clears both BSY and DRQ bits and asserts the INTRQ signal The...

Page 174: ...Interface 5 98 C141 E120 02EN g d f f d e Figure 5 7 Normal DMA data transfer ...

Page 175: ...or an Ultra DMA data out burst During an Ultra DMA burst a sender shall always drive data onto the bus and after a sufficient time to allow for propagation delay cable settling and setup time the sender shall generate a STROBE edge to latch the data Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data Words in the IDENTIFY DE...

Page 176: ...ltra DMA rules a An Ultra DMA burst is defined as the period from an assertion of DMACK by the host to the subsequent negation of DMACK b A recipient shall be prepared to receive at least two data words whenever it enters or resumes an Ultra DMA burst 5 5 3 Ultra DMA data in commands 5 5 3 1 Initiating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless o...

Page 177: ...The data in transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 3 and 5 6 3 2 for specific timing requirements 1 The device shall drive a data word onto DD 15 0 2 The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of DD 15 0 The device shall generate a DSTROBE edge no more fre...

Page 178: ...l be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the device 5 The host shall resume an Ultra DMA burst by asserting HDMARDY 5 5 3 4 Terminating an Ultra DMA data in burst a Device terminating an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise spec...

Page 179: ... host with the results of its own CRC calculation If a miscompare error occurs during one or more Ultra DMA bursts for any one command at the end of the command the device shall report the first error that occurred see 5 5 5 12 The device shall release DSTROBE within tIORDYZ after the host negates DMACK 13 The host shall not negate STOP no assert HDMARDY until at least tACK after negating DMACK 14...

Page 180: ...MARQ For this step the host may first drive DD 15 0 with the result of its CRC calculation see 5 5 5 10 If the host has not placed the result of its CRC calculation on DD 15 0 since first driving DD 15 0 during 9 the host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 11 The host shall negate DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and ...

Page 181: ... the host has negated DMACK at the end of an Ultra DMA burst 8 The host shall negate STOP within tENV after asserting DMACK The host shall not assert STOP until after the first negation of HSTROBE 9 The device shall assert DDMARDY within tLI after the host has negated STOP After asserting DMARQ and DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the h...

Page 182: ...ltra DMA burst termination when the host stops generating HSTROBE edges If the host does not assert STOP in order to initiate Ultra DMA burst termination the device shall negate DDMARDY and wait tRP before negating DMARQ 3 The host shall resume an Ultra DMA burst by generating an HSTROBE edge b Device pausing an Ultra DMA data out burst 1 The device shall not pause an Ultra DMA burst until at leas...

Page 183: ...after the device has negated DMARQ No data shall be transferred during this assertion The device shall ignore this transition on HSTROBE HSTROBE shall remain asserted until the Ultra DMA burst is terminated 6 The host shall place the result of its CRC calculation on DD 15 0 see 5 5 5 7 The host shall negate DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has n...

Page 184: ...e shall not assert DMARQ again until after the Ultra DMA burst is terminated 6 The host shall assert STOP with tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 7 If HSTROBE is negated the host shall assert HSTROBE with tLI after the device has negated DMARQ No data shall be transferred during this assertion The device shall i...

Page 185: ...hall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If the two values do not match the device shall save the error and report it at the end of the command A subsequent Ultra DMA burst for the same command that does not have a...

Page 186: ...ollowing table describes recommended values for series termination at the host and the device Table 5 17 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 22 ohm 82 ohm DIOW STOP 22 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 22 ohm 82 ohm DD15 through DD0 33 ohm 33 ohm DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY DDM...

Page 187: ...register selection setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 50 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns t11 Tim...

Page 188: ...ming parameter Min Max Unit t0 Cycle time 120 ns tC Delay time from DMACK assertion to DMARQ negation 35 ns tD Pulse width of DIOR DIOW 70 ns tE Data setup time for DIOR 30 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns tJ DMACK hold time for DIOR DIOW 5 ns tK Continuous time of high level for DIOR DIOW 2...

Page 189: ...ating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 11 Initiating an Ultra DMA data in burst DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tUI tENV tFS tENV tZAD tFS tZAD...

Page 190: ... 4 6 Data hold time at recipient from STROBE edge until data may become invalid 2 5 tDVS 70 48 31 20 6 7 4 8 Data valid setup time at sender from data valid until STROBE edge 3 tDVH 6 2 6 2 6 2 6 2 6 2 4 8 Data valid hold time at sender from STROBE edge until data may become invalid 3 tCS 15 10 7 7 5 5 CRC word setup time at device 2 tCH 5 5 5 5 5 5 CRC word hold time device 2 tCVS 70 48 31 20 6 7...

Page 191: ...egation tSS 50 50 50 50 50 50 Time from STROBE edge to negation of DMARQ or assertion of STOP when sender terminates a burst 1 Except for some instances of tMLI that apply to host signals only the parameters tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent to respond with a signal before proceedi...

Page 192: ...2 tDVHIC 9 9 9 9 9 6 Sender IC data valid hold time from STROBE edge until data may become invalid 2 1 The correct data value shall be captured by the recipient given input data with a slew rate of 0 4 V ns rising and falling and the input STROBE with a slew rate of 0 4 V ns rising and falling at tDSIC and tDHIC timing as measured through 1 5V 2 The parameters tDVSIC and tDVHIC shall be met for lu...

Page 193: ...hasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 12 Sustained Ultra DMA data in burst DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDS tDSIC tDH tDHIC t2CYC tCYC tDVS tDVSIC tDVH tDVHIC tDH tDHIC...

Page 194: ...tes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 After negating HDMARDY the host may receive zero one two or three more data words from the device Figure 5 13 Host pausing an Ultra DMA data in burst tRP tRFS DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device ...

Page 195: ...a DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Device terminating an Ultra DMA data in burst DMARQ device DMACK host DD 15 0 HDMARDY host DSTROBE device STOP host DA0 DA1 DA2 CS0 CS1 tMLI tLI tLI tLI tACK tACK tIORDYZ tSS tZAH tAZ tCVS tCVH CRC tACK ...

Page 196: ...MA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Host terminating an Ultra DMA data in burst DMARQ device tLI tMLI tRP tZAH tAZ tRFS tLI tMLI tCVS tCVH tACK tACK tACK tIORDYZ CRC DA0 DA1 DA2 CS0 CS1 DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 ...

Page 197: ...e Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 16 Initiating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tUI tLI tACK tACK tDVH tDVS tDZFS ...

Page 198: ...hasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 17 Sustained Ultra DMA data out burst HSTROBE at host HSTROBE at device DD 15 0 at host DD 15 0 at device t2CYC tCYC tCYC t2CYC tDVH tDVHIC tDVS tDVSIC tDVS tDVSIC tDVH tDVHIC tDH tDHIC tDS tDSIC tDH tDHI...

Page 199: ...tes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 After negating DDMARDY the device may receive zero one two or three more data words from the host Figure 5 18 Device pausing an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tRP tRFS ...

Page 200: ...tra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Host terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host tLI tLI tSS tLI tMLI tACK tIORDYZ tACK tACK tCVH tCVS CRC DA0 DA1 DA2 CS0 CS1 ...

Page 201: ... DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Device terminating an Ultra DMA data out burst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tLI tLI tRP tRFS tMLI tMLI tCVS tCVH tIORDYZ tACK tACK tACK CRC ...

Page 202: ...re reset 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP asse...

Page 203: ...C141 E120 02EN 6 1 CHAPTER 6 Operations 6 1 Device Response to the Reset 6 2 Power Save 6 3 Defect Management 6 4 Read Ahead Cache 6 5 Write Cache ...

Page 204: ...ecognizes presence of the slave device when it confirms assertion of the DASP signal Then the master device checks a PDIAG signal to see if the slave device has successfully completed the power on diagnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own ...

Page 205: ...ore the device power is turned on 6 1 2 Response to hardware reset Response to RESET hardware reset through the interface is similar to the power on reset Upon receipt of hardware reset the master device checks a DASP signal for up to 450 ms to confirm presence of a slave device The master device recognizes the presence of the slave device when it confirms assertion of the DASP signal Then the mas...

Page 206: ... 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds Max 31 sec Max 400 ms Max 30 sec Max 1 ms If presence of a slave device is confirmed PDIAG is checked for up to 31 seconds Checks DASP for up to 450 ms DASP PDIAG BSY bit Reset Status Reg BSY bit Slave device Master device Figure 6 2 Response to hardware reset Note Master Device does not check the DASP signal assertion for 2ms...

Page 207: ...e slave device shall report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device is p...

Page 208: ...ves the EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 6 sec Max 5 sec Max 1 ms If the slave d...

Page 209: ... completed 1 Active mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions A command other than power commands is issued A reset command is received 2 Idle mode In this mode circuits on the device is set to power save mode The device enters the Idle mode under the followi...

Page 210: ... is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CHECK POWER MODE command 4 Sleep mode The power consumption of the drive is minimal in this mode The drive enters only the standby mode from the sleep mode The only method to return from the standby mode is to execute a software or hardware reset The drive ...

Page 211: ...ector slip used for alternating defective sectors at formatting in shipment 2 Spare cylinder for alternative assignment used for automatic alternative assignment at read error occurrence 6 3 2 Alternating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the ...

Page 212: ...Figure 6 5 Sector slip processing 2 Alternate cylinder assignment A defective sector is assigned to the spare sector in the alternate cylinder This processing is performed when the alternate assignment is specified in the FORMAT TRACK command or when the automatic alternate processing is performed at read error occurrence Figure 6 8 shows an example where logical sector 4 is detective on head 0 in...

Page 213: ...g read error retry a read error is recovered Before automatic alternate assignment the device performs rewriting the corrected data to the erred sector and rereading If no error occurs at rereading the automatic alternate assignment is not performed An unrecoverable write error occurs during write error retry automatic alternate assignment is performed 6 4 Read Ahead Cache After read command which...

Page 214: ...r for read write commands 6 4 2 Caching operation Caching operation is performed only at issuance of the following commands The device transfers data from the data buffer to the host system at issuance of following command if following data exist in the data buffer All sectors to be processed by the command A part of data including load sector to be processed by the command When a part of data to ...

Page 215: ...ommand When all data requested by the read command are stored in the data buffer for write command hit all the device transfers data from the data buffer for write command At this time the read ahead operation to the data subsequent to the requested data is not performed Even if a part of data requested by the read command are stored in the data buffer for write command hit partially all data are ...

Page 216: ...equested data is not stored in the data buffer The requested data is read from the disk media The read ahead operation is performed only when the last sector address of the previous read command and the lead sector address of this read command is sequential see item 2 1 Sets the host address pointer HAP and the disk address pointer DAP to the lead of segment Segment only for read DAP HAP 2 Transfe...

Page 217: ...o the previous read command the disk drive starts the read ahead operation a Sequential command just after non sequential command When the previously executed read command is an non sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk drive assumes the received command is a sequential command and ...

Page 218: ...e read ahead operation for all area of segment with overwriting the requested data Finally the cache data in the buffer is as follows Start LBA Last LBA DAP HAP Read ahead data b Sequential hit When the previously executed read command is the sequential command and the last sector address of the previous read command is sequential to the lead sector address of the received read command the disk dr...

Page 219: ...head data 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data DAP HAP Hit data New read ahead data Read ahead data 3 After completion of data transfer of hit data the disk drive performs the read ahead operation for the data area of which the disk drive transferred hit data Read ahea...

Page 220: ...arts transferring the requested data from the address of which the requested data is stored After completion of command a previously existed cache data before the full hit reading are still kept in the buffer and the disk drive does not perform the read ahead operation 1 In the case that the contents of the data buffer is as follows for example and the previous command is a sequential read command...

Page 221: ...ot perform the read ahead operation after data transfer Following is an example of partially hit to the cache data Last LBA Cache data 1 The disk drive sets the HAP to the address where the partially hit data is stored and sets the DAP to the address just after the partially hit data HAP DAP Partially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data fr...

Page 222: ... by the host system At this time if the write operation of the previous command is still been executed the drive continuously executes the write operation of the next command from the sector next to the last sector of the previous write operation Thus the latency time for detecting a target sector of the next command is eliminated This shortens the access time The drive generates an interrupt of c...

Page 223: ...he write cache function is operated with the following command WRITE SECTOR S WRITE MULTIPLE WRITE DMA When Write Cache is permitted the writing of the data transferred from the host by the above mentioned Write Cache permit command into the disk medium may not be completed at the moment a normal ending interrupt has occurred In case a non recoverable error has occurred during receiving more than ...

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Page 225: ... The physical specifications of the drive do not always correspond to these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command ...

Page 226: ...e spindle motor is stopped and circuits other than the interface control circuit are sleeping The drive enters sleep mode when the host issues the SLEEP command Reserved Reserved bits bytes and fields are set to zero and unusable because they are reserved for future standards Rotational delay Time delay due to disk rotation The mean delay is the time required for half a disk rotation The mean dela...

Page 227: ...rmation posted from the drive to the host when command execution is ended The status indicates the command termination state VCM Voice coil motor The voice coil motor is excited by one or more magnets In this drive the VCM is used to position the heads accurately and quickly ...

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Page 229: ...ter DRDY Drive ready DRQ Ddata request bit DSC Drive seek complete DWF Drive write fault E ECC Error checking and correction ER Error register ERR Error F FR Feature register H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed ...

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Page 231: ... F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 22 7 Minami Ooi 6 Chome Shinagawa Ku Tokyo 140...

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Page 233: ...MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES PRODUCT MANUAL C141 E120 02EN MHN2300AT MHN2200AT MHN2150AT MHN2100AT DISK DRIVES PRODUCT MANUAL C141 E120 02EN ...

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