FujiFilm FinePix F30, Service Manual

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3. Schematics
FinePix F30 Service Manual
3-3. Description of Main Block Functions
3-3-1. Technical Overview
The new 6th Generation Super CCD HR captures more light from the superb Fujinon lens more efficiently with less light loss,
and sends the image to the processor with less noise. The new RP Processor II featuring enhanced double noise reduction
lets users take full advantage of the phenomenal ISO 3200 sensitivity of the FinePix F30. Other improvements include
“Intelligent Flash” and upgraded signal processing for more accurate color reproduction.
All these enhancements add up to more stunning photos every time you press the shutter.
CCD signal processing/Camera circuit section
„ Analog signals output from the 1/1.7 type Super-CCD Honeycom VI HR (IC951), with an effective pixel count of 6.3
mega-pixels, undergo false color compensation processing, adaptive interpolation processing, amplification (AGC) and
signal mixing inside the CCD signal processing IC “BCS_MCM (IC102)” before being converted to 14-bit digital signals
(A/D) and sent to the signal processing LSI “NCS_L (IC201)”.
„
The CCD drive circuit, H drive, and V drive are installed in [BCS_MCM (IC102)].
Motor Circuit Section
„ The signal processing LSI “NCS_L (IC201)” that has received various operating switch commands manages the motor
drive IC (IC151) and controls the AF, SHUTTER, ZOOM and IRIS motors.
Imaging and Signal Processing Section
„ Input data from the CCD
14-bit digital image data (corresponding to 1H) that has been output from the imaging section (CCD/Camera Block) is
sent to the signal processing LSI “NCS_L (IC201)”, converted to 32-bit (16-bit x 2) data by the [internal buffer] inside this
LSI, and the image data for one frame (2848 x 2136 pix) is stored temporarily in [SD-RAM]. It is also integrated in the
[AUTO operation section] using the 32-bit the signal processing LSI “NCS_L (IC201)” image data and sent to the
BCS_MCM (IC102) to obtain the appropriate AE/AF/AWB.
„
Record processing to xD Card
Image data stored in SD-DRAM is sent one frame at a time to the internal [signal processing section] in the signal
processing LSI “NCS_L (IC201)”. In a process called unpacking, “32-bit to 12-bit conversion” and “pre-processing
including digital clamp, white balance and noise reduction processing, linear matrix processing, gamma correction and R/
G/B 14-bit to R/G/B 8-bit conversion” to “8-bit digital R/G/B signals to Y:Cb:Cr = 4:2:2 YC processing” are implemented in
this [signal processing section] and 8-bit Y/Cb/Cr image data are sent to the [internal buffer].
The “rearrangement of data in a format in which 8-bit Y/Cb/Cr signals are easily compressed” is done in the [internal
buffer] and after passing through the [JPEG operation block] to the [media controller], they are recorded on the xD card.
„
Reproduction of images from xD card
Compressed image data from the xD card is sent as 8-bit image data to the signal processing LSI “NCS_L (IC201)” then
it is sent to the [media control section], the [DMA unit] and the SD-DRAM and then it is sent to the [media controller], to
the [JPEG operation section] and to the [signal processing section].
In the [signal processing section], 8-bit Y/Cb/Cr signals are converted to 8-bit R/G/B signals and at the same time,
lettering display signals are weighted and passed through the [LCD controller to the LCD unit and displayed.
„ Image capture system adjustment data are stored in the Flash ROM.
LCD Unit
„ Digital signals sent from the signal processing LSI “NCS_L (IC201)” are sent directly to the LCD.
Power Supply Section
„
Power supply circuits constructed in the core of the DC IC (IC300) create the following power supplies, which are
supplied to each block.
D3.3V
[IC601 (LCD BLOCK), IC151 (MOTOR BLOCK), IC551 (IPS2), IC201 (NCS_L), IC501 (CHG)]
5V [IC102 (BCS), IC601 (LCD BLOCK), IC151 (MOTOR BLOCK), IC551 (IPS2),
IC901 (LED BLOCK)]
-8V [IC102 (BCS), IC951 (CCD)]
15V [IC102 (BCS), IC951 (CCD)]
CAM3.3V [IC102 (BCS)]
1.0V [IC201 (NCS_L)]
2.5V [IC201 (NCS_L)]
DC_3.3V [IC151 (MOTOR BLOCK), IC701 (AUDIO BLOCK)]
AD_3.1V [IC201 (NCS_L), IC751 (VIDEO BLOCK)]