QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-10
Freescale Semiconductor
2.2.2
QE S08 core
This section provides summary information about the registers, addressing modes and core features. The
generated source and object-code is compatible with the M68HC08 CPU.
The S08 MCU supports only the user programming model.
Figure 2-14
shows five CPU registers. These
registers are not part of the memory map.
Figure 2-14. CPU Registers
Accumulator -- The accumulator is a general-purpose 8-bit register. One operand input to the arithmetic
logic unit (ALU) is connected to the accumulator and the ALU results are
often stored in the accumulator after arithmetic and logical operations.
Index Register (H:X) -- This is a two separate 8-bit register, which often works together as a 16-bit
address pointer where H holds the upper byte of an address and X the lower
byte. All the indexing addressing mode instructions use the 16-bit register.
Stack pointer (SP) -- This 16-bit address pointer register points to the next available location on the
automatic last-in-first-out (LIFO). The stack is used to automatically store
the return address from subroutine calls or return from interrupts. It stores
the context in the interrupt service routine (ISR) and it stores the local
variables and parameters in function calls.
Program counter (PC) -- This register contains the next instruction or operand to be retrieved. This
register automatically increments to the next memory location during a
normal program execution.
Condition code register (CCR) -- This 8-bit condition code register contains the interrupt mask (I) and
five flags that indicate the results of the instruction just executed. Bits 5 and
6 are permanently set to 1.
