QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-8
Freescale Semiconductor
The processor performs the following operations to process an exception:
Figure 2-12. Processor Operations Process
Interrupts are treated as lowest-priority exception type. CPU samples for halts and interrupts once per
instruction. The first instruction in ISR does not sample. Interrupts are guaranteed to be recoverable
exceptions.
ColdFire architecture reserves 64 entries for processor exceptions and the remaining 192 entries for I/O
interrupts. The ColdFire V1 core architecture only uses a relatively small number of the I/O interrupt
vector.
Table 2-4
shows the ColdFire V1 core processor with the exception of the vector table.
31 30 29 28
27
26
25 24 23 22 21 20 19 18
17
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Format
FS[3:2]
Vector
FS[1:0]
Status Register
Program Counter
Figure 2-13. Exception Stack Frame Form
Saves a copy of the SR.
Forces:
SR[S]=1
SR[T]=0
If an interrupt forces
the interrupt
SR[M]=0
then sets
SR[I]=to the level of
Calculates the vector for
all internal exceptions.
For interrupts, the CPU
uses the vector number
supplied by the interrupt
controller or performs an
interrupt acknowledge
(IACK) cycle to retrieve
the I/O vector number.
Init
Saves the content at the
time of the exception by
storing a 64-bit
exception stack frame
(including the saved SR)
on the top of the
supervisor stack.
The processor fetches a
32-bit vector address
from the exception
vector table @ (VBR +
vector_number x 4). The
address defines the first
instruction of the
exception handler or
interrupts service routine
(ISR). Control is then
passed to the exception
handler at this address.
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End
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