PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4
48
Freescale Semiconductor
Frequently Asked Questions (FAQs)
8.2
What should I do if the flash (NOR flash) image on the RDB is
accidentally erased?
You should set the RDB to use a hardcoded reset configuration and reprogram the flash memory by
debugger (for example, CodeWarrior de USBTAP). To use a hardcoded reset configuration, set
DIP switch S3 as OFF-ON-OFF-OFF (1011). On the other hand, if there is a reset configuration in NAND
Flash or the I
2
C EEPROM, you may want to use either one as a hard reset configuration source.
Alternatively, some REVA3 and all later boards have the I
2
C EEPROM bootloader programmed. It can be
used to reprogram the NOR Flash memory without a debugger. The procedure is as follows:
1. Power off the board and set DIP switch S3 as ON-OFF-ON-ON (0100).
2. Connect the board to Kermit (a UART terminal program; the other terminal program does not
work at this mode). Kermit can be downloaded from http://kermit.wwarthen.com/Download.htm.
3. Set the baud rate in Kermit as 38400 bps (for a 66 MHz clock-in RDB) or 19200 bps (for a 33
MHz clock-in RDB).
4. Power on the board and you should see the following in Kermit:
Hello and welcome to I2C BOOTLOADER
## Ready for binary (kermit) download
5. Go to Kermit
→
Send and select the u-boot image binary to be written into flash memory.
6. Wait for the file transfer and flash programming until you see
success
in the Kermit window.
7. Power off the board and set DIP switch S3 back to ON-ON-ON-ON (0000).
8. Power on the board and you should see a running u-boot.
REVA4
Fixes the second drawback point of REVA3.
REVB
• Added GTX_CLK125 sourced from external 125 MHz oscillator.
• Added an optional IEEE 1588 connector (P10).
• Added three more resistor options (R311–R313) to route 3 IEEE 1588 signals that only available in eTSEC1
to the IEEE 1588 connector.
• Changed S4 to support LB_POR_CFG_BOOT_ECC_DIS.
• Changed SD chip select signal from SPISEL(GPIO31) to GPIO13.
REVC
• Added a Marvell 88E1111 PHY. Phy address assigned to 0x3. Use same IRQ3# as L2 Switch.
• Added resistor option for RGMII signals route to either to L2 Switch or Marvell 88E1111 PHY.
• Added SGMII support for eTSEC1 if using the added Marvell 88E1111 PHY. (SGMII for eTSEC2 already
supported.)
• Added PLL CY23EP05SXC-1 U86 to PHY gerneated 125 MHz clock.
• Changed default TSEC1_GTX_CLK125 clock source to PLL CY23EP05SX-1 instead of external 125 MHZ
oscillator.
• Changed U36 1A linear regulator MIC39100-2.5WS to 3A MIC37302WR for higher 2.5V power consumption
by additional PHY.
• Changed default DAC to 16-bit SPI controlled MAX5 (U47).
Table 24. MPC8313E-RBD Revisions
Revision
Description
