3.2 Interrupts (Operation)
This section explains the hardware and software operation of interrupts on the device.
3.2.1 Interrupt Hardware Operation
The Interrupt Controller controls and prioritizes a maximum of 128 internal and external
interrupt sources.
Each source can be enabled or disabled by configuring the Interrupt Enable Register or
using the Interrupt Enable/Disable Number Registers. When an interrupt source is
enabled and the corresponding interrupt source is asserted, the Interrupt Controller asserts
a normal or a fast interrupt request depending on the associated Interrupt Type Register
settings.
Interrupt Controller registers can only be accessed in supervisor mode. The Interrupt
Controller interrupt requests are prioritized in the following order: fast interrupts and
normal interrupts for the highest priority level, then highest source number with the same
priority. There are 16 normal interrupt levels for all interrupt sources, with level zero
being the lowest priority. The interrupt levels are configurable through eight normal
interrupt priority level registers. Those registers, along with the Normal Interrupt Mask
Register, support software-controlled priority levels for normal interrupts and priority
masking.
3.2.2 Interrupt Software Operation
For ARM-based processors, normal interrupt and fast interrupt are two different
exception types. The exception vector addresses can be configured to start at low address
(0x0) or high address (0xFFFF0000).
The ARM Linux implementation chooses the high vector address model.
The following file describes the ARM interrupt architecture.
<ltib_dir>/rpm/BUILD/linux/Documentation/arm/Interrupts
The software provides a processor-specific interrupt structure with callback functions
defined in the irqchip structure and exports one initialization function, which is called
during system startup.
Interrupts (Operation)
i.MX 6SoloLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
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Freescale Semiconductor, Inc.
