Term
Definition
AUDMUX
Digital audio MUX-provides a programmable interconnection for voice, audio, and synchronous data routing
between host serial interfaces and peripheral serial interfaces
BCD
Binary Coded Decimal
bus
A path between several devices through data lines
bus load
The percentage of time a bus is busy
CODEC
Coder/decoder or compression/decompression algorithm-used to encode and decode (or compress and
decompress) various types of data
CPU
Central Processing Unit-generic term used to describe a processing core
CRC
Cyclic Redundancy Check-Bit error protection method for data communication
CSI
Camera Sensor Interface
DFS
Dynamic Frequency Scaling
DMA
Direct Memory Access-an independent block that can initiate memory-to-memory data transfers
DPM
Dynamic Power Management
DRAM
Dynamic Random Access Memory
DVFS
Dynamic Voltage Frequency Scaling
EMI
External Memory Interface-controls all IC external memory accesses (read/write/erase/program) from all the
masters in the system
Endian
Refers to byte ordering of data in memory. Little endian means that the least significant byte of the data is
stored in a lower address than the most significant byte. In big endian, the order of the bytes is reversed
EPIT
Enhanced Periodic Interrupt Timer-a 32-bit set and forget timer capable of providing precise interrupts at
regular intervals with minimal processor intervention
FCS
Frame Checker Sequence
FIFO
First In First Out
FIPS
Federal Information Processing Standards-United States Government technical standards published by the
National Institute of Standards and Technology (NIST). NIST develops FIPS when there are compelling
Federal government requirements such as for security and interoperability but no acceptable industry
standards
FIPS-140
Security requirements for cryptographic modules-Federal Information Processing Standard 140-2(FIPS 140-2)
is a standard that describes US Federal government requirements that IT products should meet for Sensitive,
but Unclassified (SBU) use
Flash
A non-volatile storage device similar to EEPROM, where erasing can be done only in blocks or the entire chip.
Flash path
Path within ROM bootstrap pointing to an executable Flash application
Flush
Procedure to reach cache coherency. Refers to removing a data line from cache. This process includes
cleaning the line, invalidating its VBR and resetting the tag valid indicator. The flush is triggered by a software
command
GPIO
General Purpose Input/Output
hash
Hash values are produced to access secure data. A hash value (or simply hash), also called a message
digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and is
generated by a formula in such a way that it is extremely unlikely that some other text produces the same hash
value.
I/O
Input/Output
ICE
In-Circuit Emulation
IP
Intellectual Property
ISR
Interrupt Service Routine
Table continues on the next page...
Audience
i.MX 6SoloLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
18
Freescale Semiconductor, Inc.
