Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of DSP56F803EVM - KIT EVALUATION FOR DSP56F803
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DSP56F803EVM User Manual, Rev. 5
2-8
Freescale Semiconductor
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG2. Reference
Table 2-4
for this jumper’s selection options.
2.7.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P2, allows the 56F803 to communicate with a
Parallel Printer Port on a Windows PC; see
Figure 2-5
. By using this connector, the user
can download programs and work with the 56F803’s registers.
Table 2-5
shows the
pin-out for this connector. When using the parallel JTAG interface, the jumper at JG2
should be removed; refer to
Table 2-4
. A jumper, JG8, is provided to allow the on-board
Host Target Interface to be powered by the Target board instead of the Host system, as
shown in
Table 2-6
.
Table 2-3. JTAG Connector Description
J1
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
NC
14
TRST
Table 2-4. Parallel JTAG Interface Disable Jumper Selection
JG2
Comment
No jumper
On-board Parallel JTAG Interface Enabled
1–2
Disable on-board Parallel JTAG Interface
25 / 69
25 / 69
