Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of DSP56F803EVM - KIT EVALUATION FOR DSP56F803
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DSP56F803EVM User Manual, Rev. 5
2-6
Freescale Semiconductor
2.4 Clock Source
The 56F803EVM uses an 8.00MHz crystal, Y1, connected to its External Crystal Inputs, EXTAL
and XTAL. The 56F803 uses its internal PLL to multiply the input frequency by 10 to achieve its
80MHz maximum operating frequency. An external oscillator source can be connected to the
controller by using the oscillator bypass connectors, JG3 and JG9; see
Figure 2-3
.
Figure 2-3. Schematic Diagram of the Clock Interface
2.5 Operating Mode
The 56F803EVM provides a boot-up MODE selection jumper, JG4. This jumper is used to select
the operating mode of the controller as it exits RESET. Refer to the DSP56F801-7 User’s Manual
for a complete description of the chip’s operating modes.
Table 2-2
shows the two operation
modes available on the 56F803.
Table 2-2. Operating Mode Selection
Operating Mode
JG4
Comment
0
1–2
Bootstrap from internal memory (GND)
3
No Jumper
Bootstrap from external memory (+3.3V)
56F803
EXTERNAL
OSCILLATOR
HEADERS
JG3
3
2
1
1
2
EXTAL
XTAL
JG9
8.00MHz
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