21
2
21
5.8.
On power sequence, when Vdimm is ready.
5.9.
On power sequence, but 1.05V PCH cannot ready.
5.A.
On power sequence, when 1.05V PCH is ready.
5.B.
On power sequence, but 1.1V VTT cannot ready.
5.D.
On power sequence, when 1.1V VTT is ready.
5.F.
On power sequence, but ATXPWROK cannot ready.
6.0.
On power sequence, when ATXPWROK is ready.
6.1.
On power sequence, but Vcore cannot ready.
6.6.
Power sequence finished.
2. AMI bIoS8TM Check Point
1. Bootblock Initialization Code Checkpoints
The Bootblock initialization code sets up the chipset, memory and other components before
system memory is available. The following table describes the type of checkpoints that may
occur during the bootblock initialization portion of the BIOS:
Checkpoint
Description
Before D0
If boot block debugger is enabled, CPU cache-as-RAM functionality is
enabled at this point. Stack will be enabled from this point.
D0
Early Boot Strap Processor (BSP) initialization like microcode update,
frequency and other CPU critical initialization. Early chipset initialization is
done.
D1
Early super I/O initialization is done including RTC and keyboard controller.
Serial port is enabled at this point if needed for debugging. NMI is disabled.
Perform keyboard controller BAT test. Save power-on CPUID value in scratch
CMOS. Go to flat mode with 4GB limit and GA20 enabled.
D2
Verify the boot block checksum. System will hang here if checksum is bad.
D3
Disable CACHE before memory detection. Execute full memory sizing
module. If memory sizing module not executed, start memory refresh and do
memory sizing in Boot block code. Do additional chipset initialization.
Re-enable CACHE. Verify that flat mode is enabled.
D4
Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5
Bootblock code is copied from ROM to lower system memory and control is
given to it. BIOS now executes out of RAM. Copies compressed boot block
code to memory in right segments. Copies BIOS from ROM to RAM for faster
access. Performs main BIOS checksum and updates recovery status
accordingly.
Checkpoints may differ between different platforms based on system configuration.
Checkpoints may change due to vendor requirements, system chipset or option ROMs
from add-in PCI devices.
CA
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IO
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