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Forlinx FET6254-C, Hardware Manual

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Forlinx FET6254-C Hardware Manual Download Page 63

Hardware manual

OK6254-C FET6254-C

www.forlinx.net

- 63 -

note: analog signal reflow zone and digital signal reflow zone should be separated on PCB layout to avoid
serial interference.

3.5.15 RTC

Recommended RTC battery model: CR2023

3.5.16 QSPI Flash

Main domain and MCU domain which one to be mounted to QSPI Flash could be controlled by jumper
wire.

Summary of Contents for FET6254-C

Page 1: ...FET6254 C OK6254 C ARM Cortex A53 ARM Cortex M4F Embedded Development Platform Hardware Manual Rev 1 0 July 2022 Forlinx Embedded Technology Co Ltd www forlinx net User Manual...

Page 2: ...Hardware manual OK3568 C FET3568 C www forlinx net 2 Update record Date Manual version SoM version Carrier board version Update record July 2022 V1 0 V1 1 V1 1 First edition...

Page 3: ...nt 10 2 3 4 SoM Interface Speed 11 2 4 SoM Resource 11 2 5 SoM FET6254 C Pin Definition 13 2 5 1 Schematic 13 2 5 2 SoM FET6254 C Pins Spec 16 2 6 SoM Pin Spec 25 2 6 1 Power Pin 25 2 6 2 Boot Pin 27...

Page 4: ...3 5 4 Debug Port 53 3 5 5 JTAG 53 3 5 6 LED and User Key 54 3 5 7 Display 55 3 5 8 Video Input 57 3 5 9 TF Card 57 3 5 10 Ethernet 58 3 5 11 USB 59 3 5 12 4G 5G 60 3 5 13 WiFi BT 61 3 5 14 Audio 62 3...

Page 5: ...uct in dusty or untidy conditions Please do not use or store the product in alternate cold and hot conditions to avoid condensing which will damage components Please do not treat the product rudely An...

Page 6: ...are manual OK6254 C FET6254 C www forlinx net 6 Copyright Announcement Please note that reproduction of this User Manual in whole or in part without express written permission from Forlinx is not perm...

Page 7: ...users to solve the problems 3 Accesses to Technical Support 3 1 If you are able to understand Chinese you can try to all the technical persons directly the tel number non instant messenger is 0086 312...

Page 8: ...one internal port and two external ports with Time Sensitive Networking TSN support An additional PRU module on the device enables real time I O capability for customer s own use cases In addition th...

Page 9: ...Hardware manual OK6254 C FET6254 C www forlinx net 9 Chapter 2 Introduction of FET6254 C SoM 2 1 FET6254 C Exterior 2 2 FET6254 C Mechanical Dimensions Top layer bottom layer 3...

Page 10: ...four corners which could be used for reinforcement purpose in case of vibration circumstances Users can take Forlinx designing for reference use M2 L 2mm mounting nuts as below 2 3 FET6254 C Features...

Page 11: ...bps Ethernet 2 RMII 10 100 or RGMII 10 100 1000 Supports IEEE1588 Annex D Annex E Annex F with 802 1AS PTP Supports TSN Supports hardware IP UDP TCP verify and unload USB 2 USB2 0 up to 480Mbps Can be...

Page 12: ...0B or ISO 11898 1 protocols Supports complete CAN FD up to 64 bytes Supports RAM parity ECC Rating up to 5Mbps SD 2 2x 4 bit SD SDIO up to UHS I Complies with eMMC5 1 SD3 0 and SDIO3 0 GPMC 1 Up to 1...

Page 13: ...Hardware manual OK6254 C FET6254 C www forlinx net 13 2 5 SoM FET6254 C Pin Definition 2 5 1 Schematic...

Page 14: ...Hardware manual OK6254 C FET6254 C www forlinx net 14...

Page 15: ...Hardware manual OK6254 C FET6254 C www forlinx net 15...

Page 16: ...C www forlinx net 16 2 5 2 SoM FET6254 C Pins Spec Note Subscript Spec 1 PIN can be configured to interrupt 2 The default power is 1 8V 3 PINsarerelatedtoCPU boot not recommended to be used as IO 4 De...

Page 17: ...DS data A3 CH1_LVDS_A3P 29 CH1_LVDS_A3N CH1_LVDS data A3 CH1_LVDS_A3N 31 GND Ground GND 33 CH2_LVDS_CLKN CH2_LVDS clock _ CH2_LVDS_CLKN 35 CH2_LVDS_CLKP CH2_LVDS clock CH2_LVDS_CLKP 37 GND Ground GND...

Page 18: ...22 CSI0_RXP2 MIPI_CSI0 receive data 2 CSI0_RXP2 24 CSI0_RXN2 MIPI_CSI0 receive data 2 CSI0_RXN2 26 GND Ground GND 28 CSI0_RXP0 MIPI_CSI0 receive data 0 CSI0_RXP0 30 CSI0_RXN0 MIPI_CSI0 receive data 0...

Page 19: ...T0 WKUP_CLKOUT0 31 GND Ground GND 33 1 8 MCU domain ESM error MCU_SAFETY_ERROR 35 CONN_MCU_POR 3 3 MCU domain cold reset CONN_MCU_PORZ 37 MCU_RESETZ 3 3 MCU domain warm reset MCU_RESETZ 39 MCU_RESETST...

Page 20: ...5 36 B13 SPI0_D0 GPIO1_18 3 3 main domain SPI0 data 0 GPIO1_18 38 A14 SPI0_CLK GPIO1_17 3 3 main domain SPI0 clock GPIO1_17 40 B14 SPI0_D1 GPIO1_19 3 3 main domain SPI0 data 1 GPIO1_19 42 GND Ground G...

Page 21: ...CPSW_RGMII1_TX_CTL 37 GND Ground GND 39 AE20 CPSW_RGMII1_TD0 GPIO0_75 3 3V RGMII1 transmit data 0 CPSW_RGMII1_TD0 41 AD20 CPSW_RGMII1_TD1 GPIO0_76 3 3V RGMII1 transmit data 1 CPSW_RGMII1_TD1 43 AE18 C...

Page 22: ...VOUT0_DATA12 38 AA24 VOUT0_DATA1 GPIO0_58 3 3V Video output data 13 VOUT0_DATA13 40 Y22 VOUT0_DATA1 GPIO0_59 3 3V Video output data 14 VOUT0_DATA14 42 AA21 VOUT0_DATA1 GPIO0_60 3 3V Video output data...

Page 23: ...k clock input OSPI0_LBCLK 35 GND Ground GND 37 J24 OSPI_DQS GPIO0_2 1 8 OSPI data strobe or OSPI_DQS 39 GND Ground GND 41 H24 OSPI_CLK GPIO0_0 1 8 OSPI clock output OSPI_CLK 43 GND Ground GND 45 U23 G...

Page 24: ...and MMC2_CMD 30 D25 MMC2_CLK GPIO0 1 8 MMC2 clock MMC2_CLK 32 GND Ground GND 34 B24 MMC2_DATA0 GPIO0 1 8 MMC2 data 0 MMC2_DATA0 36 C25 MMC2_DATA1 GPIO0 1 8 MMC2 data 1 MMC2_DATA1 38 A23 GPIO0_71 GPIO0...

Page 25: ...power supplying pin 5V P4_76 DCDC_5V Power input Som power supplying pin 5V P4_78 DCDC_5V Power input Som power supplying pin 5V P4_80 GND P1_1 GND P1_2 GND P1_7 GND P1_8 GND P1_13 GND P1_14 GND P1_1...

Page 26: ...P1_79 GND P1_80 GND P2_1 GND P2_2 GND P2_7 GND P2_8 GND P2_17 GND P2_18 GND P2_27 GND P2_30 GND P2_31 GND P2_41 GND P2_42 GND P2_47 GND P2_48 GND P2_61 GND P2_62 GND P2_71 GND P2_75 GND P2_80 GND P2_...

Page 27: ...D P4_66 GND P4_68 GND P4_70 GND P4_75 GND P4_79 2 6 2 Boot Pin Pin Signal I O Default function Pin NO BOOTMODE BOOTMODE00 I Boot mode 0 P3_78 BOOTMODE01 I Boot mode 1 P3_76 BOOTMODE02 I Boot mode 2 P3...

Page 28: ...DS clock P1_33 CH2_LVDS_CLKP O CH2_LVDS clock P1_35 CH2_LVDS_A1N O CH2_LVDS data 1 P1_39 CH2_LVDS_A1P O CH2_LVDS data 1 P1_41 CH2_LVDS_A2N O CH2_LVDS data 2 P1_45 CH2_LVDS_A2P O CH2_LVDS data 2 P1_47...

Page 29: ...RGMII receiving data 3 P3_29 CPSW_RGMII1_TXC O RGMII sending clock P3_33 CPSW_RGMII1_TX_CTL O RGMII sending control P3_35 CPSW_RGMII1_TD0 O RGMII sending data 0 P3_39 CPSW_RGMII1_TD1 O RGMII sending...

Page 30: ...ripheral Signal I O Default function Pin No CPTS CP_GEMAC_CPTS0_RFT_CLK O CPTS reference clock input LD_72 CP_GEMAC_CPTS0_TS_COMP I CPTS from CPSW3G0 CPTS timestamp counter compare output LD_70 UART3...

Page 31: ...VOUT0_DATA13 O Video output data 13 P3_38 VOUT0_DATA14 O Video output data 14 P3_40 VOUT0_DATA15 O Video output data 15 P3_42 VOUT0_DATA16 O Video output data 16 P3_60 VOUT0_DATA17 O Video output dat...

Page 32: ...ta 21 P3_50 TRC_DATA22 O Trace data 22 P3_52 TRC_DATA23 O Trace data 23 P3_54 MCU Domain Peripheral Signal I O Default function Pin No JTAG EMU0 IO Emulation control 0 P2_43 EMU1 IO Emulation control...

Page 33: ...index P2_72 EQEP1_S IO EQEP latch P2_74 EQEP2 EQEP2_A I EQEP quadrature input A P3_59 P2_50 EQEP2_B I EQEP quadrature input B P3_61 P2_52 EQEP2_I IO EQEP index P3_75 P2_44 P4_47 EQEP2_S IO EQEP latch...

Page 34: ...non multiplexed mode address 23 output under A D multiplexed mode P3_24 GPMC0_A8 OZ GPMC address 8 output under A D non multiplexed mode address 24 output under A D multiplexed mode P3_28 GPMC0_A9 OZ...

Page 35: ...GPMC data 0 input output under A D non multiplexed mode and extra address 1 output under A D multiplexed mode P3_78 GPMC0_AD1 IO GPMC data 1 input output under A D non multiplexed mode and extra addre...

Page 36: ...multiplexed mode and extra address 14 output under A D multiplexed mode P3_50 GPMC0_AD14 IO GPMC data 14 input output under A D non multiplexed mode and extra address 15 output under A D multiplexed m...

Page 37: ...N Main Domain Peripheral Signal I O Pin No MCAN0 MCAN0_RX I P2_46 MCAN0_TX O P2_44 MCU Domain Peripheral Signal I O Pin No MCU_MCAN0 MCU_MCAN0_RX I P2_4 MCU_MCAN0_TX O P2_6 MCU_MCAN1 MCU_MCAN1_RX I P2...

Page 38: ...MCASP1_AXR5 IO P4_30 P4_57 MCASP2 MCASP2_ACLKR IO P3_73 P3_46 MCASP2_ACLKX IO P3_77 P2_69 P3_50 MCASP2_AFSR IO P3_57 P3_48 MCASP2_AFSX IO P2_67 P3_75 P3_52 MCASP1_AXR0 IO P3_59 P2_44 P3_60 MCASP1_AXR1...

Page 39: ...p Select 1 P2_32 SPI0_CS2 IO SPI Chip Select 2 P2_67 SPI0_CS3 IO SPI Chip Select 3 P2_69 SPI0_D0 IO SPI data 0 P2_36 SPI0_D1 IO SPI data 1 P2_40 MCSP1 SPI1_CLK IO SPI clock P4_25 SPI1_CS0 IO SPI chip...

Page 40: ...SPI1_CLK IO SPI clock P2_12 P2_3 MCU_SPI1_CS0 IO SPI chip select 0 P2_10 MCU_SPI1_CS1 IO SPI Chip Select 1 P2_5 MCU_SPI1_CS2 IO SPI Chip Select 2 P2_16 P2_3 MCU_SPI1_CS3 IO SPI Chip Select 3 P2_4 MCU_...

Page 41: ...SPI MAIN Domain Function Signal name I O PIN number OSPI OSPI0_CLK O P4_41 OSPI0_DQS I P4_37 OSPI0_ECC_FAIL I P4_9 OSPI0_LBCLKO IO P4_33 OSPI0_CSn0 O P4_3 OSPI0_CSn1 O P4_5 OSPI0_CSn2 O P4_7 OSPI0_CSn...

Page 42: ...60 1 The default function of this pin is I2C0 and multiple devices are mounted on SoM so it is suspended MCU Domain Function Signal name I O PIN number System Signal MCU_ERRORn IO P2_33 MCU_EXT_REFCLK...

Page 43: ...TIMER_IO6 IO P2_67 P4_10 TIMER_IO7 IO P2_69 P4_20 MCU Domain Function Signal name I O PIN number MCU_TIMER MCU_TIMER_IO0 IO P2_13 P2_4 MCU_TIMER_IO1 IO P2_15 P2_28 MCU_TIMER_IO2 IO P2_5 MCU_TIMER_IO3...

Page 44: ...UART1_RXD I P2_54 P2_74 UART1_TXD O P2_56 P2_72 UART2 UART2_CTSn I P2_16 P3_4 P3_48 UART2_RTSn O P3_3 P4_18 P3_46 UART2_RXD I P2_67 P4_6 P3_60 P3_10 UART2_TXD O P2_69 P4_4 P3_58 P3_12 UART3 UART3_CTS...

Page 45: ..._7 P3_48 P3_22 UART5_TXD O P3_24 P2_46 P4_24 P4_9 P3_46 UART6 UART6_CTSn I P3_34 P4_29 UART6_RTSn O P4_27 P3_32 UART6_RXD I P2_70 P4_10 P4_30 P4_23 P3_28 P4_47 UART6_TXD O P2_68 P4_20 P4_28 P4_25 P4_6...

Page 46: ...TSn O P2_12 WKUP_UART0_RXD I P2_14 WKUP_UART0_TXD O P2_16 2 7 SoM Designing Tips FET6254 C SoM mounted with power reset monitoring circuit and storage circuit About the minimum system schematic please...

Page 47: ...Hardware manual OK6254 C FET6254 C www forlinx net 47 Chapter 3 OK6254 C Carrier Board Features 3 1 Overview...

Page 48: ...ingle LVDS output mode 2x single LVDS copy output mode two LVDS output same content dual LVDS output mode 8 lane data and 2 lane clock combine to one output channel Default and recommended model Forli...

Page 49: ...al and alternative 4G M 2 Key B 4G module recommended model Quectel EM05 default EC20 5G M 2 Key B 5G module recommended model Quectel RM500U CN Standard MicroSIM card slot WiFi 1 On boardAW CM358M IE...

Page 50: ...ed by POWER_EN it s up pulled to SoM 3 3V by 100K resistor and will be released when the SoM critical power is finished VCC_3V3 supplies power to all 3 3V carrier board devices VCC_5V is controlled by...

Page 51: ...d to the key 3 5 3 Boot Mode GPMC0_AD0 GPMC0_AD15 on SoM are respectively for BOOTMODE00 BOOTMODE15 BOOTMODE Pin Mapping 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Reserved Backup Boot Mode Config...

Page 52: ...selected booting mode It s configured to BOOTMODE 13 0 on SoM BOOTMODE 14 15 preserved pins it s configured to BOOTMODE 14 15 00 on SoM Primary Boot Mode Selection OK6254 C can support multiplex boot...

Page 53: ...oM Forlinx takes U7 for UART signal buffer Note 1 We kindly users have the debug ported designed when designing carrier board which will be much convenient and necessary 2 U7 is just reference circuit...

Page 54: ...onsist of main domain and MCU domain Main domain integrates LED and user key together What should be noticed is that when test GPIO output please don t press the key otherwise it will forcibly pull GP...

Page 55: ...upport wo LVDS and one RGB parallel output Two LVDS ports are available on P16 by 2x 19P pin headers with pitch of 2 0mm which can be mounted with Forlinx 10 1 LVDS display One RGB parallel port on P1...

Page 56: ...54 C FET6254 C www forlinx net 56 TP reset and interrupt signals of both 7 LCD and 10 1 LVDS display are 3 3V while the four GPIO of CPU are 1 8V so power converting is needed and also the signals are...

Page 57: ...one MIPI DPHY 4Lanes input it s available on carrier board by P15 2x10P 2 0mm pin headers for 4 Lanes backup And by P13 26P with pitch of 0 5mm for 2 Lanes FPC for Forlinx OV5645 module Note 1 IIC po...

Page 58: ...rlinx net 58 Note 1 TF card power supply should be controlled please refer to Forlinx carrier board circuit 2 Impedance single end 50ohm 3 5 10 Ethernet There are two 10 100 1000M Ethernet ports avail...

Page 59: ...omplete reference plane 3 The two PHY chips are mounted to the same MDC MDIO please notice that the addresses should not be conflict 4 Equal length requirement RGMII receiving end and sending end shou...

Page 60: ...ost mode and device mode could be controlled by DIP S3 OFF for Device mode and ON for Host mode Note 1 It needs to add ESD protection to the data line 2 impedance requirement differential 90ohm 3 5 12...

Page 61: ...Hardware manual OK6254 C FET6254 C www forlinx net 61 3 5 13 WiFi BT There is CAM358 WIFI BT module available on carrier board...

Page 62: ...ardware manual OK6254 C FET6254 C www forlinx net 62 Note Impedance single end 50ohm 3 5 14 Audio The carrier board is integrated with ES8388 audio codec chip can support earphone output and MIC input...

Page 63: ...reflow zone and digital signal reflow zone should be separated on PCB layout to avoid serial interference 3 5 15 RTC Recommended RTC battery model CR2023 3 5 16 QSPI Flash Main domain and MCU domain...

Page 64: ...802 11 a b g n ac dual band WiFi up to 433 3Mbps and BT5 up to 3Mbps To strengthen signal please use a 2 4G 5GHz WiFi antenna Note audio function is not available for BT SD signal should be equal leng...

Page 65: ...board has two CAN FD and one RS485 available on it One CAN FD for Main domain and one for MCU domain Note 1 CAN and RS485 should be with necessary solution for EMC testing if no EMC testing or just n...

Page 66: ...ease refer to Forlinx carrier board circuit 3 5 19 EEPROM MCU domain and WKUP domain which one to be mounted to EEPROM could be controlled by jumper wire 3 5 20 MCU Pins for Users MCU pins for users a...

Page 67: ...ns are 1 8V which should be noticed 4 power supply to TF card should be under control 5 display interface and USB device power consumption is relative high please notice specially about the PCB circui...

Page 68: ...age V Working current mA Instantaneous peak stable value OK6254 C Evk Unloaded power on 12 293 234 Loaded with LVDS LCD 12 649 590 Loaded with LVDS LCD cpu occupies 90 12 800 770 SoM only Unloaded pow...

Page 69: ...Hardware manual OK6254 C FET6254 C www forlinx net 69...

Page 70: ...Hardware manual OK6254 C FET6254 C www forlinx net 70 Connector model for carrier board is AXK5F80537YG...

Page 71: ...Hardware manual OK6254 C FET6254 C www forlinx net 71 Appendix 4 Minimum System Schematic...

Page 72: ...Hardware manual OK6254 C FET6254 C www forlinx net 72...

Page 73: ...Hardware manual OK6254 C FET6254 C www forlinx net 73 The minimum system contains SoM power OS flashing circuit and serial debug circuit...

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