Hardware manual
OK6254-C FET6254-C
www.forlinx.net
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BOOTMODE12
I
Boot mode 12
P3_52
BOOTMODE13
I
Boot mode 13
P3_50
BOOTMODE14
I
Boot mode 14
P3_48
BOOTMODE15
I
Boot mode 15
P3_46
2.6.3 LVDS Output Pin
MAIN Domain
Pin
Signal
I/ O
Default function
Pin NO.
LVDS
CH1_LVDS_A0P
O
CH1_LVDS data 0+
P1_3
CH1_LVDS_A0N
O
CH1_LVDS data 0-
P1_5
CH1_LVDS_A1P
O
CH1_LVDS data 1+
P1_9
CH1_LVDS_A1N
O
CH1_LVDS data 1-
P1_11
CH1_LVDS_A2P
O
CH1_LVDS data 2+
P1_15
CH1_LVDS_A2N
O
CH1_LVDS data 2-
P1_17
CH1_LVDS_CLKP
O
CH1_LVDS clock+
P1_21
CH1_LVDS_CLKN
O
CH1_LVDS clock-
P1_23
CH1_LVDS_A3P
O
CH1_LVDS data 3+
P1_27
CH1_LVDS_A3N
O
CH1_LVDS data 3-
P1_29
CH2_LVDS_CLKN
O
CH2_LVDS clock-
P1_33
CH2_LVDS_CLKP
O
CH2_LVDS clock+
P1_35
CH2_LVDS_A1N
O
CH2_LVDS data 1-
P1_39
CH2_LVDS_A1P
O
CH2_LVDS data 1+
P1_41
CH2_LVDS_A2N
O
CH2_LVDS data 2-
P1_45
CH2_LVDS_A2P
O
CH2_LVDS data 2+
P1_47
CH2_LVDS_A0P
O
CH2_LVDS data 0+
P1_51
CH2_LVDS_A0N
O
CH2_LVDS data 0-
P1_53
CH2_LVDS_A3P
O
CH2_LVDS data 3+
P1_57
CH2_LVDS_A3N
O
CH2_LVDS data 3-
P1_59
Backlight control
EHRPWM1_A
O
EHRPWM1_A
P2_66
2.6.4 MIPI CSI
MAIN Domain
Pin
Signal
I/ O
Default function
Pin NO.
MIPI CSI
CSI0_RXCLKP
I
CSI0 clock +
P1_4
CSI0_RXCLKN
I
CSI0 clock -
P1_6
CSI0_RXP3
I
CSI0 data receiving 3+
P1_10
CSI0_RXN3
I
CSI0 data receiving 3-
P1_12
CSI0_RXP1
I
CSI0 data receiving 1+
P1_16
CSI0_RXN1
I
CSI0 data receiving 1-
P1_18
CSI0_RXP2
I
CSI0 data receiving 2+
P1_22
CSI0_RXN2
I
CSI0 data receiving 2-
P1_24
CSI0_RXP0
I
CSI0 data receiving 0+
P1_28
CSI0_RXN0
I
CSI0 data receiving 0-
P1_30
Summary of Contents for FET6254-C
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Page 71: ...Hardware manual OK6254 C FET6254 C www forlinx net 71 Appendix 4 Minimum System Schematic...
Page 72: ...Hardware manual OK6254 C FET6254 C www forlinx net 72...
