Forlinx FET6254-C, Hardware Manual

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Hardware manual
OK6254-C FET6254-C
www.forlinx.net
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EHRPWM0_SYNCO O Synchronously output from external pin to P2_56
EPWM1
EHRPWM1_A IO EHRPWM output A
P2_38,
P2_66
EHRPWM1_B IO EHRPWM output B
P2_36,
P2_64
EPWM2
EHRPWM2_A IO
EHRPWM output A
P2_54,
P2_63
EHRPWM2_B IO
EHRPWM output B
P2_56,
P2_65,
2.6.12 EQEP
MAIN Domain
Peripheral Signal I/O Default function Pin No.
EQEP0
EQEP0_A I EQEP quadrature input A P2_70
EQEP0_B I EQEP quadrature input B P2_68
EQEP0_I IO EQEP index P2_64
EQEP0_S IO EQEP latch P2_66
EQEP1
EQEP1_A I EQEP quadrature input A P2_78
EQEP1_B I EQEP quadrature input B P2_76
EQEP1_I IO EQEP index P2_72
EQEP1_S IO EQEP latch P2_74
EQEP2
EQEP2_A I EQEP quadrature input A
P3_59,
P2_50
EQEP2_B I EQEP quadrature input B
P3_61,
P2_52
EQEP2_I IO EQEP index
P3_75,
P2_44,
P4_47
EQEP2_S IO EQEP latch
P3_77,
P2_46,
P4_71
2.6.13 GPMC
Main domain
Pin Signal I/ O Default function Pin NO.
GPMC
GPMC0_ADVn_ALE O
GPMC address valid(low power valid) or address
latch enable
P4_67
GPMC0_CLK O GPMC clock P4_77
GPMC0_DIR O GPMC data bus signal direction control P4_71
GPMC0_OEn_REn O
GPMC output enable(low power valid) or read
enable(low power valid)
P4_65
GPMC0_WEn O GPMC write enable(low power enable) P4_63
GPMC0_WPn O GPMC Flash write protection(low power valid) P4_61
GPMC0_A0 OZ
GPMC address 0 output. Only for valid
addressing 8-bit data non-multiplexed memory
P3_10
GPMC0_A1 OZ GPMC address 1 output under A/ D P3_12