Optional PMBus Addressing
Alternatively the PMBus address can be defined by
connecting the SA0/SA1 pins according to the table below.
SA1 = open for products with no SA1 pin.
SA0
low
open
high
SA1
low
20h
21h
22h
open
23h
24h
25h
high
26h
27h
Reserved
Low = Shorted to PREF
Open = High impedance
High = Logic high, GND as reference,
Logic High definitions see Electrical Specification
Reserved Addresses
Address 4Bh is allocated for production needs and cannot be
used.
Addresses listed in the table below are reserved or assigned
according to the SMBus specification and may not be usable.
Refer to the SMBus specification for further information.
Address
(decimal) Comment
0
General Call Address / START byte
1
CBUS address
2
Address reserved for different bus format
3-7
Reserved for future use
8
SMBus Host
9-11
Assigned for Smart Battery
12
SMBus Alert Response Address
40
Reserved for ACCESS.bus host
44-45 Reserved by previous versions of the SMBus
specification
55
Reserved for ACCESS.bus default address
64-68 Reserved by previous versions of the SMBus
specification
72-75 Unrestricted addresses
97
SMBus Device Default Address
120-123 10-bit slave addressing
124-127 Reserved for future use
I
2
C/SMBus – Timing
Setup and hold times timing diagram
The setup time, t
set
, is the time data, SDA, must be stable
before the rising edge of the clock signal, SCL. The hold time
t
hold
, is the time data, SDA, must be stable after the falling
edge of the clock signal, SCL. If these times are violated
incorrect data may be captured or meta-stability may occur
and the bus communication may fail. When configuring the
product, all standard SMBus protocols must be followed,
including clock stretching. Refer to the SMBus specification,
for SMBus electrical and timing requirements.
This product does not support the BUSY flag in the status
commands to indicate product being too busy for SMBus
response. Instead a bus-free time delay according to this
specification must occur between every SMBus transmission
(between every stop & start condition). In case of storing the
RAM content into the internal non-volatile memory (commands
STORE_USER_ALL and STORE_DEFAULT_ALL) an
additional delay of 100 ms has to be inserted. A 100 ms delay
should be inserted after a restore from internal non-volatile
memory (commands RESTORE_DEFAULT_ALL and
RESTORE_USER_ALL).
BMR4
6
series
PoL Regulators
Input 4.5-14 V, Output up to 50 A / 165 W
1/28701-BMR 464 Rev.B
July 2019
© Flex
Technical Specification
BMR4
6
series
PoL Regulators
Input
4.5-14
V, Output up to
50
A
/
165
W
1/28701-BMR 464 Rev.B
July 2019
©
Flex
Technical Specification
68
