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Flex BMR464, Manual

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Flex BMR464 Manual Download Page 37

Ericsson Internal 

PRODUCT SPECIFICATION 

16 (20)

Prepared (also subject responsible if other) 

No. 

EHOSMIR 

2/1301-BMR 464 0008 Uen 

Approved 

Checked 

Date 

Rev 

Reference 

EAB/FJB/GM (Ksenia Harrisen) 

(EKRIROB)  2014-05-02 

C 

 

 

Typical Characteristics

Load Transient 

BMR 464 2008 (SIP)

Load Transient vs. External Capacitance, V

O 

= 1.0 V 

Load Transient vs. External Capacitance, V

O 

= 3.3 V 

Load transient peak voltage deviation vs. external capacitance.  

Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,  

T

P1

 = +25 °C. V

I 

= 12 V, V

O 

= 1.0 V, f

sw 

= 320 kHz, di/dt = 2 A/µs 

Load transient peak voltage deviation vs. external capacitance.  

Step (12.5-37.5-12.5 A). Parallel coupling of capacitors with 470 µF/10 mΩ,  

T

P1

 = +25 °C. V

I

= 12 V, V

O

= 3.3 V, f

sw

= 320 kHz, di/dt = 2 A/µs

 

Load transient vs. Switch Frequency 

Output Load Transient Response, Default Configuration 

Load transient peak voltage deviation vs. frequency.  

Step-change (12.5-37.5-12.5 A). 

T

P1

 = +25 °C. V

I 

= 12 V, V

O 

= 1.0 V, C

O 

= 470 µF/10 mΩ 

Output voltage response to load 

Step-change (12.5-37.5-12.5 A) at: 

T

P1

 = +25 °C, V

I

 = 12 V, V

O

 = 1.0 V 

di/dt = 2 A/µs, f

sw 

= 320 kHz 

C

O 

= 470 µF/10 mΩ 

Top trace: output voltage (200 mV/div.). 

Bottom trace: load current (10 A/div.). 

Time scale: (0.1 ms/div.). 

Note 1: For Universal PID, see section Dynamic Loop Compensation (DLC). 

Note 2: In these graphs, the worst-case scenario (load step 37.5-12.5 A) has been considered. 

0

100

200

300

400

500

0

1

2

3

4

5

[mV]

[mF]

Universal PID,

No NLR
DLC,

No NLR
Universal PID,

Default NLR
DLC,

Default NLR
Universal PID,

Opt. NLR
DLC,

Opt. NLR

0

100

200

300

400

500

0

1

2

3

4

5

[mV]

[mF]

Universal PID,

No NLR
DLC,

No NLR
Universal PID,

Default NLR
DLC,

Default NLR
Universal PID,

Opt. NLR
DLC,

Opt. NLR

0

100

200

300

400

500

600

200

300

400

500

600

[mV]

[kHz]

Universal PID,

No NLR
DLC,

No NLR
Universal PID,

Default NLR
DLC,

Default NLR
Universal PID,

Opt. NLR
DLC,

Opt. NLR

BMR4

6

 series

 PoL Regulators

Input 4.5-14 V, Output up to 50 A / 165 W

1/28701-BMR 464  Rev.B   

         July 2019

© Flex

Technical Specification

BMR4

6

 series

 PoL Regulators

Input 

4.5-14

 V, Output up to 

50

 A

 

/

 165

 W

1/28701-BMR 464  Rev.B   

         July 2019

© 

Flex

Technical Specification

37

Summary of Contents for BMR464

Page 1: ...eries PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification INTERNAL USE ONLY TABLE OF CONTENTS 1 1 Prepared Subject resp No BPOW 00201 00152 Uen Approved Document resp Checked Date Rev 7 10 2009 PD1 D Contents Ordering Information 2 General Information 2 Safety Specification 3 Absolute Maximum Ratings 4 Electrical Specification 40A 0 6 3...

Page 2: ...011 65 EU and have a maximum concentration value of 0 1 by weight in homogeneous materials for lead mercury hexavalent chromium PBB and PBDE and of 0 01 by weight in homogeneous materials for cadmium Exemptions in the RoHS directive utilized in Flex products are found in the Statement of Compliance document Flex fulfills and will continuously fulfill all its obligations under regulation EC No 1907...

Page 3: ...ff see Mechanical Information for further information It is the responsibility of the installer to ensure that the final product housing these components complies with the requirements of all applicable safety standards and regulations for the final product Component power supplies for general use shall comply with the requirements in IEC EN UL 62368 1 Product related standards e g IEEE 802 3af Po...

Page 4: ...oduct is designed with a digital control circuit The control circuit uses a configuration file which determines the functionality and performance of the product The Electrical Specification table shows parameter values of functionality and performance with the default configuration file unless otherwise specified The default configuration file is designed to fit most application needs w ith focus ...

Page 5: ...ternal resistance S S to VOUT GND 4 7 Ω Line regulation VO 0 6 V 2 mV VO 1 0 V 3 VO 1 8V 3 VO 3 3 V 3 Load regulation IO 0 100 VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8V 2 VO 3 3 V 2 VOac Output ripple noise CO 470 μF minimum external capacitance See Note 11 VO 0 6 V 15 mVp p VO 1 0 V 20 VO 1 8 V 25 VO 3 3 V 35 IO Output current See Note 18 0 001 40 A IS Static input current at max IO VO 0 6 V 2 45 A VO 1 0...

Page 6: ...PWM Duty Cycle 5 95 Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source 13 13 Input Under Voltage Lockout UVLO UVLO threshold 3 85 V UVLO threshold range PMBus configurable 3 85 14 V Set point accuracy 150 150 mV UVLO hysteresis 0 35 V UVLO hysteresis range PMBus configurable 0 10 15 V Delay 2 5 μs Fault response See Note 3 Automatic restart 70 ms Input Over...

Page 7: ... Bus free time SMBus See Note 1 2 ms Cp Internal capacitance on logic pins 10 pF Initialization time See Note 10 35 ms Output Voltage Delay Time See Note 6 Delay duration See Note 16 10 ms Delay duration range PMBus configurable 2 500000 Delay accuracy turn on Default configuration CTRL controlled Precise timing enabled 0 25 ms PMBus controlled Precise timing disabled Current sharing operation 0 2...

Page 8: ...Procedure Note 11 See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise Note 12 See graph Load Transient vs External Capacitance and Operating information section External Capacitors Note 13 Time for reaching 100 of nominal Vout Note 14 For Vout 1 0 V accuracy is 10 mV For further deviations see section Output Voltage Adjust using PMBus Note 15 A...

Page 9: ...µF 10 mΩ Efficiency vs Output Current and Switching Frequency Power Dissipation vs Output Current and Switching frequency Efficiency vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency Dissipated power vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed fr...

Page 10: ...PID NLR Load transient peak voltage deviation vs frequency Step change 10 30 10 A TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Output voltage response to load current step change 10 30 10 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 470 µF 10 mΩ Top trace output voltage 200 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Note In the load transient graphs the worst case s...

Page 11: ... V See Thermal Consideration section Current Limit Characteristics VO 1 0 V Current Limit Characteristics VO 3 3 V Output voltage vs load current at TP1 25 C VO 1 0 V Note Output enters hiccup mode at current limit Output voltage vs load current at TP1 25 C VO 3 3 V Note Output enters hiccup mode at current limit 0 10 20 30 40 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10 20 3...

Page 12: ...0 20 40 60 80 100 2 mV 0 6 V 1 0 V 1 8 V 3 3 V 0 99 0 99 1 00 1 00 1 01 V sson Interna ODUCT SPEC 01 BMR 464 4 05 02 put Ripple ut voltage ripple at 2 V CO 470 µF 40 A put Ripple vs ut voltage ripple V 40 A Default confi d regulation regulation at Vo 200 250 300 Vpk pk 90 95 00 05 10 0 8 l CIFICATION 4 Uen Rev R C BMR Noise VO 3 t TP1 25 C 10 mΩ T T s Frequency Vpk pk at TP1 25 guration except ch ...

Page 13: ... 0 V CO 470 µF 10 mΩ IO 40 A Top trace output voltage 0 5 V div Bottom trace input voltage 5 V div Time scale 2 ms div Start up by CTRL signal Shut down by CTRL signal Start up by enabling CTRL signal at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ IO 40 A Top trace output voltage 0 5 V div Bottom trace CTRL signal 5 V div Time scale 20 ms div Shut down enabled by disconnecting VI at TP1 25 C VI 12 V...

Page 14: ...al resistance S S to VOUT GND 4 7 Ω Line regulation VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8V 2 VO 3 3 V 2 Load regulation IO 0 100 VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8V 2 VO 3 3 V 2 VOac Output ripple noise CO 470 μF minimum external capacitance See Note 11 VO 0 6 V 20 mVp p VO 1 0 V 25 VO 1 8 V 30 VO 3 3 V 45 IO Output current See Note 18 0 001 40 A IS Static input current at max IO VO 0 6 V 2 46 A VO 1 0 V 3...

Page 15: ...PWM Duty Cycle 5 95 Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source 13 13 Input Under Voltage Lockout UVLO UVLO threshold 3 85 V UVLO threshold range PMBus configurable 3 85 14 V Set point accuracy 150 150 mV UVLO hysteresis 0 35 V UVLO hysteresis range PMBus configurable 0 10 15 V Delay 2 5 μs Fault response See Note 3 Automatic restart 70 ms Input Over...

Page 16: ... Bus free time SMBus See Note 1 2 ms Cp Internal capacitance on logic pins 10 pF Initialization time See Note 10 35 ms Output Voltage Delay Time See Note 6 Delay duration See Note 16 10 ms Delay duration range PMBus configurable 2 500000 Delay accuracy turn on Default configuration CTRL controlled Precise timing enabled 0 25 ms PMBus controlled Precise timing disabled Current sharing operation 0 2...

Page 17: ...Procedure Note 11 See graph Output Ripple vs External Capacitance and Operating information section Output Ripple and Noise Note 12 See graph Load Transient vs External Capacitance and Operating information section External Capacitors Note 13 Time for reaching 100 of nominal Vout Note 14 For Vout 1 0 V accuracy is 10 mV For further deviations see section Output Voltage Adjust using PMBus Note 15 A...

Page 18: ...0 mΩ Efficiency vs Output Current and Switching Frequency Power Dissipation vs Output Current and Switching frequency Efficiency vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency Dissipated power vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed freque...

Page 19: ...ad transient peak voltage deviation vs frequency Step change 10 30 10 A TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Output voltage response to load current step change 10 30 10 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 470 µF 10 mΩ Top trace output voltage 200 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Note In the load transient graphs the worst case scenario lo...

Page 20: ...ee Thermal Consideration section Current Limit Characteristics VO 1 0 V Current Limit Characteristics VO 3 3 V Output voltage vs load current at TP1 25 C VO 1 0 V Note Output enters hiccup mode at current limit Output voltage vs load current at TP1 25 C VO 3 3 V Note Output enters hiccup mode at current limit 0 10 20 30 40 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10 20 30 40...

Page 21: ... ripple Vpk pk at TP1 25 C VI 12 V CO 470 µF 10 mΩ IO 40 A Default configuration except changed frequency Output Ripple vs External Capacitance Load regulation VO 1 0V Output voltage ripple Vpk pk at TP1 25 C VI 12 V IO 40 A Parallel coupling of capacitors with 470 µF 10 mΩ Load regulation at Vo 1 0 V at TP1 25 C CO 470 µF 10 mΩ 0 10 20 30 40 50 5 7 9 11 13 mVpk pk V 0 6 V 1 0 V 1 8 V 3 3 V 0 20 4...

Page 22: ...CO 470 µF 10 mΩ IO 40 A Top trace output voltage 0 5 V div Bottom trace input voltage 5 V div Time scale 2 ms div Start up by CTRL signal Shut down by CTRL signal Start up by enabling CTRL signal at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ IO 40 A Top trace output voltage 0 5 V div Bottom trace CTRL signal 5 V div Time scale 20 ms div Shut down enabled by disconnecting VI at TP1 25 C VI 12 V VO 1...

Page 23: ...nal resistance S S to VOUT GND 47 Ω Line regulation VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8 V 2 VO 3 3 V 3 Load regulation IO 0 100 VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8 V 2 VO 3 3 V 2 VOac Output ripple noise CO 470 μF minimum external capacitance See Note 11 VO 0 6 V 20 mVp p VO 1 0 V 25 VO 1 8 V 30 VO 3 3 V 35 IO Output current See Note 18 0 001 50 A IS Static input current at max IO VO 0 6 V 3 10 A VO 1 0 V...

Page 24: ... Circuit PWM Duty Cycle 5 95 Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source 13 13 Input Under Voltage Lockout UVLO UVLO threshold 3 85 V UVLO threshold range PMBus configurable 3 85 14 V Set point accuracy 150 150 mV UVLO hysteresis 0 35 V UVLO hysteresis range PMBus configurable 0 10 15 V Delay 2 5 μs Fault response See Note 3 Automatic restart 70 ms I...

Page 25: ...s See Note 1 250 ns thold Hold time SMBus See Note 1 300 ns tfree Bus free time SMBus See Note 1 2 ms Cp Internal capacitance on logic pins 10 pF Initialization time See Note 10 40 ms Output Voltage Delay Time See Note 6 Delay duration See Note 16 10 ms Delay duration range PMBus configurable 5 500000 Delay accuracy turn on 0 25 4 ms Delay accuracy turn off 0 25 4 ms Output Voltage Ramp Time See N...

Page 26: ...t Ripple vs External Capacitance and Operating information section Output Ripple and Noise Note 12 See graph Load Transient vs External Capacitance and Operating information section External Capacitors Note 13 Time for reaching 100 of nominal Vout Note 14 For Vout 1 0 V accuracy is 10 mV For further deviations see section Output Voltage Adjust using PMBus Note 15 Accuracy here means deviation from...

Page 27: ...iency vs Output Current and Switching Frequency Power Dissipation vs Output Current and Switching frequency Efficiency vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency Dissipated power vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency 75 80 ...

Page 28: ...V CO 470 µF 10 mΩ Output voltage response to load current Step change 12 5 37 5 12 5 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 470 µF 10 mΩ Top trace output voltage 200 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Note 1 For Universal PID see section Dynamic Loop Compensation DLC Note 2 In the load transient graphs the worst case scenario load step 37 5 12 5 A h...

Page 29: ...Thermal Consideration section Current Limit Characteristics VO 1 0 V Current Limit Characteristics VO 3 3 V Output voltage vs load current at TP1 25 C VO 1 0 V Note Output enters hiccup mode at current limit Output voltage vs load current at TP1 25 C VO 3 3 V Note Output enters hiccup mode at current limit 0 10 20 30 40 50 20 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10 20 30...

Page 30: ... voltage ripple Vpk pk at TP1 25 C VI 12 V CO 470 µF 10 mΩ IO 50 A Default configuration except changed frequency Output Ripple vs External Capacitance Load regulation VO 1 0 V Output voltage ripple Vpk pk at TP1 25 C VI 12 V IO 50 A Parallel coupling of capacitors with 470 µF 10 mΩ Load regulation at VO 1 0 V TP1 25 C CO 470 µF 10 mΩ 0 10 20 30 40 5 7 9 11 13 mVpk pk V 0 6 V 1 0 V 1 8 V 3 3 V 0 1...

Page 31: ... V CO 470 µF 10 mΩ IO 50 A Top trace output voltage 0 5 V div Bottom trace input voltage 5 V div Time scale 2 ms div Start up by CTRL signal Shut down by CTRL signal Start up by enabling CTRL signal at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ IO 50 A Top trace output voltage 0 5 V div Bottom trace CTRL signal 2 V div Time scale 20 ms div Shut down enabled by disconnecting VI at TP1 25 C VI 12 V V...

Page 32: ...resistance S S to VOUT GND 47 Ω Line regulation VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8 V 2 VO 3 3 V 3 Load regulation IO 0 100 VO 0 6 V 2 mV VO 1 0 V 2 VO 1 8 V 2 VO 3 3 V 2 VOac Output ripple noise CO 470 μF minimum external capacitance See Note 11 VO 0 6 V 20 mVp p VO 1 0 V 25 VO 1 8 V 30 VO 3 3 V 40 IO Output current See Note 18 0 001 50 A IS Static input current at max IO VO 0 6 V 3 12 A VO 1 0 V 4 8...

Page 33: ...Circuit PWM Duty Cycle 5 95 Minimum Sync Pulse Width 150 ns Input Clock Frequency Drift Tolerance External clock source 13 13 Input Under Voltage Lockout UVLO UVLO threshold 3 85 V UVLO threshold range PMBus configurable 3 85 14 V Set point accuracy 150 150 mV UVLO hysteresis 0 35 V UVLO hysteresis range PMBus configurable 0 10 15 V Delay 2 5 μs Fault response See Note 3 Automatic restart 70 ms In...

Page 34: ...s See Note 1 250 ns thold Hold time SMBus See Note 1 300 ns tfree Bus free time SMBus See Note 1 2 ms Cp Internal capacitance on logic pins 10 pF Initialization time See Note 10 40 ms Output Voltage Delay Time See Note 6 Delay duration See Note 16 10 ms Delay duration range PMBus configurable 5 500000 Delay accuracy turn on 0 25 4 ms Delay accuracy turn off 0 25 4 ms Output Voltage Ramp Time See N...

Page 35: ...put Ripple vs External Capacitance and Operating information section Output Ripple and Noise Note 12 See graph Load Transient vs External Capacitance and Operating information section External Capacitors Note 13 Time for reaching 100 of nominal Vout Note 14 For Vout 1 0 V accuracy is 10 mV For further deviations see section Output Voltage Adjust using PMBus Note 15 Accuracy here means deviation fr...

Page 36: ...y vs Output Current and Switching Frequency Power Dissipation vs Output Current and Switching frequency Efficiency vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency Dissipated power vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency 75 80 85 9...

Page 37: ...O 1 0 V CO 470 µF 10 mΩ Output voltage response to load Step change 12 5 37 5 12 5 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 470 µF 10 mΩ Top trace output voltage 200 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Note 1 For Universal PID see section Dynamic Loop Compensation DLC Note 2 In these graphs the worst case scenario load step 37 5 12 5 A has been conside...

Page 38: ...al Consideration section Current Limit Characteristics VO 1 0 V Current Limit Characteristics VO 3 3 V Output voltage vs load current at TP1 25 C VO 1 0 V Note Output enters hiccup mode at current limit Output voltage vs load current at TP1 25 C VO 3 3 V Note Output enters hiccup mode at current limit 0 10 20 30 40 50 20 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10 20 30 40 5...

Page 39: ...O 50 A Output voltage ripple Vpk pk at TP1 25 C VI 12 V CO 470 µF 10 mΩ IO 50 A Default configuration except changed frequency Output Ripple vs External Capacitance Load regulation VO 1 0 V Output voltage ripple Vpk pk at TP1 25 C VI 12 V IO 50 A Parallel coupling of capacitors with 470 µF 10 mΩ Load regulation at VO 1 0 V TP1 25 C CO 470 µF 10 mΩ 0 10 20 30 40 5 7 9 11 13 mVpk pk V 0 6 V 1 0 V 1 ...

Page 40: ... 470 µF 10 mΩ IO 50 A Top trace output voltage 0 5 V div Bottom trace input voltage 5 V div Time scale 2 ms div Start up by CTRL signal Shut down by CTRL signal Start up by enabling CTRL signal at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ IO 50 A Top trace output voltage 0 5 V div Bottom trace CTRL signal 2 V div Time scale 20 ms div Shut down enabled by disconnecting VI at TP1 25 C VI 12 V VO 1 0...

Page 41: ... 2 VO 1 8 V 2 VO 3 3 V 2 VOac Output ripple noise CO 470 μF minimum external capacitance See Note 11 VO 0 6 V 20 mVp p VO 1 0 V 25 VO 1 8 V 30 VO 3 3 V 35 IO Output current See Note 18 0 001 50 A IS Static input current at max IO VO 1 0 V 4 9 A VO 3 3 V 14 53 Ilim Current limit threshold 52 65 A Isc Short circuit current RMS hiccup mode See Note 3 VO 0 6 V 11 A VO 1 0 V 9 VO 1 8 V 7 VO 3 3 V 6 η E...

Page 42: ...nge PMBus configurable 4 2 16 V Set point accuracy 150 150 mV IOVP hysteresis 1 V IOVP hysteresis range PMBus configurable 0 11 8 V Delay 2 5 μs Fault response See Note 3 Automatic restart 70 ms Power Good PG See Note 2 PG threshold PMBus configurable 90 VO PG hysteresis 5 VO PG delay PMBus configurable 10 s PG delay range PMBus configurable 0 500 s Output voltage Over Under Voltage Protection OVP...

Page 43: ... V 3 0 A READ_IOUT vs IO IO 0 50 A TP1 0 to 95 C VI 4 5 14 V VO 0 6 3 3 V 5 0 A Note 1 See section I2C SMBus Setup and Hold Times Definitions Note 2 Monitorable over PMBus Interface Note 3 Automatic restart 70 or 240 ms after fault if the fault is no longer present Continuous restart attempts if the fault reappear after restart See Operating Information and AN302 for other fault response options N...

Page 44: ...rent and Switching Frequency Power Dissipation vs Output Current and Switching frequency Efficiency vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency Dissipated power vs load current and switch frequency at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ Default configuration except changed frequency 75 80 85 90 95 100 0 10 2...

Page 45: ...i dt 2 A µs fsw 320 kHz CO 4000 µF Top trace output voltage 100 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Output voltage response to load current Step change 10 30 10 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 4000 µF Top trace output voltage 100 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Output Load Transient Response Opt PID default NLR ...

Page 46: ...Available load current vs ambient air temperature and airflow at VO 1 8 V VI 12 V See Thermal Consideration section Available load current vs ambient air temperature and airflow at VO 3 3 V VI 12 V See Thermal Consideration section 0 10 20 30 40 50 20 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10 20 30 40 50 20 40 60 80 100 120 A C 3 0 m s 2 0 m s 1 0 m s 0 5 m s Nat Conv 0 10...

Page 47: ...ge ripple Vpk pk at TP1 25 C VI 12 V IO 50 A Parallel coupling of capacitors with 470 µF 10 mΩ Current Limit Characteristics VO 1 0 V Current Limit Characteristics VO 3 3 V Output voltage vs load current at TP1 25 C VO 1 0 V Note Output enters hiccup mode at current limit Output voltage vs load current at TP1 25 C VO 3 3 V Note Output enters hiccup mode at current limit 0 10 20 30 40 5 7 9 11 13 m...

Page 48: ...trace input voltage 10 V div Mid trace output voltage 1V div Bottom trace PG 2 V div Time scale 10 ms div Start up by CTRL signal Shut down by CTRL signal Start up by enabling CTRL signal at TP1 25 C VI 12 V VO 1 0 V CO 470 µF 10 mΩ IO 50 A Top trace CTRL 5 V div Mid trace output voltage 1V div Bottom trace PG 2 V div Time scale 10 ms div Shut down enabled by disconnecting VI at TP1 25 C VI 12 V V...

Page 49: ...on features that continuously safeguard the load from damage due to unexpected system faults A fault is also shown as an alert on the SALERT pin The following product parameters can continuously be monitored by a host Input voltage output voltage current and internal temperature If the monitoring is not needed it can be disabled and the product enters a low power mode reducing the power consumptio...

Page 50: ...ge source contains significant inductance the addition a capacitor with low ESR at the input of the product will ensure stable operation External Capacitors Input capacitors The input ripple RMS current in a buck converter is equal to Eq 1 D D I I load inputRMS 1 where load I is the output load current and D is the duty cycle The maximum load ripple current becomes 2 load I The ripple current is d...

Page 51: ...cally takes between 50 ms and 200 ms to complete By the PMBus command AUTO_COMP_CONFIG the user may select between several different modes of operation Disable Autocomp once will run DLC algorithm each time the output is enabled default configuration Autocomp every second will initiate a new DLC algorithm each 1 second Autocomp every minute will initiate a new DLC algorithm every minute The DLC ca...

Page 52: ... The NLR settings can be reconfigured using the PMBus interface See application note AN306 for further information Remote Sense The product has remote sense that can be used to compensate for voltage drops between the output and the point of load The sense traces should be located close to the PWB ground layer to reduce noise susceptibility Due to derating of internal output capacitance the voltag...

Page 53: ... remains ON until the device attempts a restart i e the output voltage is pulled to ground level crowbar function The default response from an overvoltage fault is to immediately shut down as in 2 The device will continuously check for the presence of the fault condition and when the fault condition no longer exists the device will be re enabled For continuous OVP when operating from an external c...

Page 54: ... PMBus command in response to an observed load current change All phases modules in a current share rail are considered active prior to the current sharing rail ramp to power good Phases can be dropped after power good is reached Any member of the current sharing rail can be dropped If the reference module is dropped the remaining active module with the lowest member position will become the new r...

Page 55: ...imes of internal interface voltages in the controller circuit to approximatley 2 ms The soft start power up of the product can be reconfigured using the PMBus interface VIN CTRL VOUT Initialization time Delay time Ramp time Illustration of Power Up Procedure Output Voltage Sequencing A group of products may be configured to power up in a predetermined sequence This feature is especially useful whe...

Page 56: ... time as follows Eq 5 s 1 GCB GCB C R where GCB R is the pull up resistor value and GCB C is the bus loading The pull up resistor should be tied to an external supply voltage in range from 3 3 to 5 V which should be present prior to or during power up If exploring untested compensation or deadtime configurations it is recommended that 27 Ω series resistors are placed between the GCB pin of each pr...

Page 57: ...nge Decrease Config parameters Switching frequency Control loop bandwidth NLR threshold Diode emulation DCM Min pulse Optimized performance Maximize efficiency Enable Disable Minimize ripple ampl Enable or disable Enable or disable Improve load transient response Disable Disable Minimize idle power loss Enable Enable Note 1 The following table graphs and waveforms are only examples and valid for B...

Page 58: ... A µs Load Transient vs Decoupling Capacitance VO 3 3 V Load transient peak voltage deviation vs decoupling capacitance Step 12 5 37 5 12 5 A Parallel coupling of capacitors with 470 µF 10 mΩ TP1 25 C VI 12 V VO 3 3 V fsw 320 kHz di dt 2 A µs 70 75 80 85 90 95 0 10 20 30 40 50 A 200 kHz 320 kHz 480 kHz 640 kHz 0 2 4 6 8 10 12 0 10 20 30 40 50 W A 200 kHz 320 kHz 480 kHz 640 kHz 0 10 20 30 40 50 60...

Page 59: ... kHz CO 470 µF 10 mΩ DLC and no NLR Top trace output voltage 200 mV div Bottom trace load current 10 A div Time scale 0 1 ms div Output Load Transient Response DLC and Optimized NLR Output voltage response to load current step change 12 5 37 5 12 5 A at TP1 25 C VI 12 V VO 1 0 V di dt 2 A µs fsw 320 kHz CO 470 µF 10 mΩ DLC and optimized NLR Top trace output voltage 200 mV div Bottom trace load cur...

Page 60: ...ould not exceed the maximum temperatures in the table below The number of measurement points may vary with different thermal design and topology Temperatures above maximum TP1 measured at the reference point P1 are not allowed and may cause permanent damage It should also be noted that depending on setting of the over temperature protection OTP and operating conditions the product may shut down be...

Page 61: ...n layout bottom view component placement for illustration only Pin Designation Function 1A 1B VIN Input Voltage 2A 2B GND Power Ground 3A 3B VOUT Output Voltage 4A S Positive sense 4B S Negative sense 5A VSET Output voltage pinstrap 5B VTRK Voltage Tracking input 6A SALERT PMBus Alert 6B SDA PMBus Data 7A SCL PMBus Clock 7B SA1 PMBus address pinstrap 1 8A SA0 PMBus address pinstrap 0 8B SYNC Synch...

Page 62: ...e PMBus signals The capacitor CI or capacitors implementing it should be placed as close to the input pins as possible Capacitor CO or capacitors implementing it should be placed close to the load Care should be taken in the routing of the connections from the sensed output voltage to the S and S terminals These sensing connections should be routed as a differential pair preferably between ground ...

Page 63: ...on Top view of product footprint BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 63 ...

Page 64: ... Top view of product footprint BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 64 ...

Page 65: ...ation BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 65 ...

Page 66: ...voltage READ_VOUT Output current READ_IOUT Internal junction temperature READ_TEMPERATURE_1 Switching frequency READ_FREQUENCY Duty cycle READ_DUTY_CYCLE In the default configuration monitoring is enabled also when the output voltage is disabled This can be changed in order to reduce standby power consumption Snap shot parameter capture This product offers a special feature that enables the user t...

Page 67: ...n in the table 1 tolerance resistors are required Schematic of connection of address resistor Index RSA k Index RSA k 0 10 13 34 8 1 11 14 38 3 2 12 1 15 42 2 3 13 3 16 46 4 4 14 7 17 51 1 5 16 2 18 56 2 6 17 8 19 61 9 7 19 6 20 68 1 8 21 5 21 75 9 23 7 22 82 5 10 26 1 23 90 9 11 28 7 24 100 12 31 6 The PMBus address follows the equation below Eq 7 PMBus Address decimal 25 x SA1 index SA0 index Th...

Page 68: ... I2 C SMBus Timing Setup and hold times timing diagram The setup time tset is the time data SDA must be stable before the rising edge of the clock signal SCL The hold time thold is the time data SDA must be stable after the falling edge of the clock signal SCL If these times are violated incorrect data may be captured or meta stability may occur and the bus communication may fail When configuring ...

Page 69: ..._UC_FAULT_LIMIT 4Bh Yes Designation Cmd Impl OT_FAULT_LIMIT 4Fh Yes OT_WARN_LIMIT 51h Yes UT_WARN_LIMIT 52h Yes UT_FAULT_LIMIT 53h Yes VIN_OV_FAULT_LIMIT 55h Yes VIN_OV_WARN_LIMIT 57h Yes VIN_UV_WARN_LIMIT 58h Yes VIN_UV_FAULT_LIMIT 59h Yes Fault Response Commands VOUT_OV_FAULT_RESPONSE 41h Yes VOUT_UV_FAULT_RESPONSE 45h Yes OT_FAULT_RESPONSE 50h Yes UT_FAULT_RESPONSE 54h Yes VIN_OV_FAULT_RESPONSE...

Page 70: ...RACK_CONFIG E1h Yes PID_TAPS D5h Yes PID_TAPS_CALC F2h Yes INDUCTOR D6h Yes NLR_CONFIG D7h Yes TEMPCO_CONFIG DCh Yes IOUT_OMEGA_OFFSET BEh Yes AUTO_COMP_CONTROL BDh Yes AUTO_COMP_CONFIG BCh Yes DEADTIME DDh Yes DEADTIME_CONFIG DEh Yes DEADTIME_MAX BFh Yes SNAPSHOT EAh Yes SNAPSHOT_CONTROL F3h Yes DEVICE_ID E4h Yes USER_DATA_00 B0h Yes Group Commands SEQUENCE E0h Yes GCB_CONFIG D3h Yes GCB_GROUP E2...

Page 71: ...subject to change throughout the product s life cycle unless explicitly described and dimensioned in this drawing BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 71 ...

Page 72: ...ect to change throughout the product s life cycle unless explicitly described and dimensioned in this drawing BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 72 ...

Page 73: ...o change throughout the product s life cycle unless explicitly described and dimensioned in this drawing BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification BMR46 series PoL Regulators Input 4 5 14 V Output up to 50 A 165 W 1 28701 BMR 464 Rev B July 2019 Flex Technical Specification 73 ...

Page 74: ... products only depending on the type of solder paste and flux system used on the host board up to a recommended maximum temperature of 245 C could be used if the products are kept in a controlled environment dry pack handling and storage prior to assembly Lead free Pb free solder processes For Pb free solder processes a pin temperature TPIN in excess of the solder melting temperature TL 217 to 221...

Page 75: ...verheating A no clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board The cleaning residues may affect long time reliability and isolation voltage Delivery Package Information Laydown version The products are delivered in antistatic carrier tape EIA 481 standard Carrier Tape Specifications Material Antistatic PS Su...

Page 76: ... seconds in order to prevent overheating A no clean flux is recommended to avoid entrapment of cleaning fluids in cavities inside the product or between the product and the host board The cleaning residues may affect long time reliability and isolation voltage Delivery Package Information SIP version The products are delivered in antistatic trays Tray Specifications Material Antistatic Polyethylen...

Page 77: ...oisture reflow sensitivity 1 J STD 020C Level 1 SnPb eutectic Level 3 Pb Free 225 C 260 C Operational life test MIL STD 202G method 108A Duration 1000 h Resistance to soldering heat 2 IEC 60068 2 20 Tb method 1A Solder temperature Duration 270 C 10 13 s Robustness of terminations IEC 60068 2 21 Test Ua1 IEC 60068 2 21 Test Ue1 Through hole mount products Surface mount products All leads All leads ...

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