User Manual
DIC324
NOTE:
Table 3-14: Register of outputs
Address
D7
D6
D5
D4
D3
D2
D1
D0
BA + 0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
3.3.3
Module identification
TheFPGA1 has its own identifier, which coincides with the code of the diagram, loaded to the
FPGA. The identifier could be read via the byte ports with addresses BA+Eh, BA+Fh (where BAx
–
base address of the FPGA1).
NOTE:
THE MODULE IS DELIVERED WITH A WORKING CODE OF THE "D11"
DIAGRAM BY DEFAULT.
SOME VERSIONS OF THE DIAGRAMS LOADED TO THE FPGA MAY NOT HAVE
ITS OWN IDENTIFIER (SHALL BE ADDITIONALLY AGREED IN THE RELEVANT
TEXT FILES OF DESCRIPTIONS OF THE LOADED DIAGRAMS' VERSIONS).
Register of the diagram code identifier is available through the byte ports with addresses
BA+Eh, BA+Fh.
Designation of register bits for ports with addresses BA+Eh, BA+Fh is shown in the tables
below.
Table 3-15: Port (BA+Eh) through reading
Bit
Notation
Conventions
Purpose
D0
–D7
‘a … z’
ASCII code of Latin capital letters from “a” to “z”
1)
1)
Identifier letter (conventional symbol of the diagram type): “c” – counters, “f” –
frequency meters, “g” – signal generators, “t” – timers, “x” – special custom options of
diagrams.
Table 3-16: Port (BA+Fh) through reading
Bit
Notation
Conventions
Purpose
D0
–D7
SN[7:0]
Diagram number code from “0” to “255”
1)
1)
Identifier digits (sequence number of the diagram type):
Programming example for reading the FPGA1 identifier in “C” language shall be viewed as
follows:
printf ("DIC324 Diagram Code:\"D11\"
FASTWEL, 2016\n");
// -- Determine Base Address ---- for
(BA=0x110;BA<0x400;BA+=0x10)
if ((inportb(BA+0xA00E)=='D')&&(inportb(BA+0xA00F)==11)) break;
if (BA==0x400) { printf("Diagram Code\"D11\"not loaded !");return;
} else printf("Base address of DIC324 module is
determined:%Xh\n",BA);
NOTE:
THE MODULE IS DELIVERED WITH A WORKING CODE OF THE "D11" DIAGRAM BY
DEFAULT.
NOTE:
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