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Functional Description
CPB902
C P B 9 0 2 U s e r M a n u a l
63
© 2 0 0 8 F a s t w e l v . 1 . 5 b E
4.3.15 FBUS
Connector
FBUS is an interface bus, which enables CPB902 to be a part of FBUS networks. FBUS interface
controller is routed to J22 (one row, 6-pin, 2 mm pitch) on-board connector. FBUS physical level is
identical to the one of RS485 interface. The addresses 0x312–0x314 are used to manipulate the
FBUS controller. The J22 contacts assignment is given in Table 4.21.
Table 4.21:
FBUS Connector J22 Pinout
Pin #
Signal
Pin #
Signal
1
D+
4
HISPEED
2
D-
5
GND
3
DAISY OUT
6
GND
4.3.16
RTC and Serial FRAM
The module is equipped with a standard Real Time Clock. FRAM is non-volatile memory with I2C
serial interface. It serves as a back-up storage for BIOS Setup parameters and for restoration of
the RTC memory if an error is detected. Free FRAM memory units (7 KB) are available to the user
via INT17H BIOS function. See also
in BIOS Setup description.
For long-term storage of the CPB902 module the on-board battery can be disconnected by
removing the jumper from the J19 contacts 1-2 (see next subsection).
4.3.17
J19
Configuration
Jumpers
Some of the system configuration jumpers are integrated at the J19 pinpad. They allow switching
between main and reserve BIOS copies and connect/disconnect the RTC battery. The J19 circuit
diagram is shown in Figure 4.29 and the jumpers' function is given in Table 4.22 below.
Figure 4.29:
J19 Circuit Diagram
Battery1
To RTC
1
2
3
4
To ROM BIOS (SA18)
+5V
J19
Table 4.22:
J19 Pins Designation
Jumper Position
Function
1-2
Closed: RTC battery is connected; open: the battery is disconnected
3-4
When closed, the reserve BIOS copy is enabled (EEPROM lower addresses area).
When open, the main BIOS copy is enabled (EEPROM high addresses area)