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Functional Description
CPB902
C P B 9 0 2 U s e r M a n u a l
61
© 2 0 0 8 F a s t w e l v . 1 . 5 b E
Figure 4.26:
Discrete I/O Channel Block Diagram
+5 V (max)
Load
I
max
= 20 m
А
SD
C1
Output port (T rigger)
SD
Input port
OE
FPGA
1
315h, 316h (W)
315h, 316h (R)
316h, 31Bh (R)
Figure 4.27:
Discrete I/O Unit: Ports Binding Diagram
KEY_C1
KEY_C0
KEY_R5
KEY_R4
KEY_R3
KEY_R2
KEY_R1
KEY_R0
KEY_C3
KEY_C2
KEY_C5
KEY_C4
Read/Write port 316h
D0
D1
D2
D3
Read/Write port 315h
D0
D1
D2
D3
D4
D5
D6
D7
D4
D5
D6
D7
Triggers State Read Port 316h
D0
D1
D2
D3
D4
D5
D6
D7
Triggers State Read Port 31Bh
C1
C0
R5
R4
R3
R2
R1
R0
C3
C2
C5
C4
C3
C2
C5
C4
C1
C0
R5
R4
R3
R2
R1
R0