Functional Description
CPB902
C P B 9 0 2 U s e r M a n u a l
26
© 2 0 0 8 F a s t w e l v . 1 . 5 b E
Table 4.3:
System I/O ports (FPGA)
Port
(hex)
Bit
Read
Write
Value
Comment
0
0
yes
yes
1
0
1
yes
yes
1
0
2
yes
yes
1
0
3
yes
yes
1
0
4
yes
yes
1
0
5
yes
yes
1
0
6
yes
yes
1
0
300
7
yes
yes
1
NAND flash: read/write data, write address, write commands
0
yes
no
0
1
yes
no
0
–
0
2
yes
no
1
FL_RB line status reading (NAND FLASH not available)
0
/CE NAND FLASH line set to 0
3
yes
yes
1
/CE NAND FLASH line set to 1
0
/WP NAND FLASH line set to 0
4
yes
yes
1
/WP NAND FLASH line set to 1
5
yes
no
0
Reserved. Permanent logic “0”
0
ALE NAND FLASH line set to 0
6
yes
yes
1
ALE NAND FLASH line set to 1
0
CLE NAND FLASH line set to 0
301
7
yes
yes
1
CLE NAND FLASH line set to 1
0
0
yes
no
1
Opto-IRQ line status reading
1
2
3
4
5
6
302*
7
0
0
yes
yes
1
/PDOWN_VIDEO line status set/read
0
1
yes
no
1
WDT_READ line status: read
0
2
yes
yes
1
WDT_RES line status: set/read
0
3
yes
no
1
/SV_PFO line status: read
0
4
yes
yes
1
/PC104_MEMW line mask bit status: set/read
(1 – Set mask, 0 – Clear mask)
0
5
yes
yes
1
/SV_PFO line mask bit status: set/read
(1 – Set mask, 0 – Clear mask)
0
6
yes
yes
1
KEY_R[5…0] and KEY_C[5...0] lines switching between matrix
keypad and discrete I/O units.
0 – Matrix keypad unit connected to
KEY_R[5…0] and KEY_C[5...0] lines
1 – Discrete I/O unit connected to
KEY_R[5…0] and KEY_C[5...0] lines
310*
7
yes
no
0
–
