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Static levels compatibility
(LV)TTL Driver
Logic Level
(LV)TTL Driver
Voltage Level
Isolated-Input
Voltage Level
Voltage Margin
Isolated Input
Logic Level
Low
0.4 V max
1.5 V max
1.1 V
Low
High
2.4 V min
1.9 V min
0.5 V
High
The above table shows that the voltage levels are well compatible and that they remains
acceptable voltage margins for both TTL and LVTTL applications.
See also:
"Isolated Input (Version 1)" on page 148
in the hardware manual for electrical
specifications of isolated inputs.
NOTE
Note the circuit does not perform logic level inversion.
NOTE
The isolated input needs about 1 mA of current at high logic level. This is
compatible with the current drive capabilities of (LV)TTL drivers at, as most
(LV)TTL drivers pr/-16 mA. Even old TTL technologies provides 4 mA
min in any case.
Dynamic limitations
Isolated inputs requires a minimum pulse high of 10 µs. The highest achievable pulse rate is 50
KHz.
Isolated inputs adds an extra delay of typically 5 µs (10 µs maximum).
NOTE
The delay can be sometimes ignored and sometimes not, according to the
application.
For probably all the area-scan applications, such delay can be ignored, as is it
very short compared to the camera cycle. For instance, such delay represents
only 0.5 % of the cycle time of a super-fast 1,000 fps camera.For line-scan
applications, the delay becomes significant since the camera cycle rate is
much higher.
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Hardware Manual
