Ericsson KPC-300, Maintenance Manual, Page: 10 / 34

Synthesizer
The synthesizer circuit generates all transmit and receive
RF frequencies. This circuit consists of synthesizer IC U302,
temperature compensated crystal oscillator (TCXO) U303,
voltage controlled oscillator (VCO) U301 and associated
loop filter circuitry.
The VCO operates at the transmitter frequency during
transmit function and 45 MHz above the receive frequency
during the receive function. The synthesizer is controlled by
the CPU. Frequency stability is maintained by the TCXO
module.
A portion of the VCO output is applied to the synthesizer
IC and divided by 65/64 dual modulus prescaler, which is
set by pulse swallow counter A and programmable counter
B to provide a 5 kHz or 6.25 kHz output for comparison with
a reference signal. The reference signal is derived from the
12.8 MHz TCXO module. The synthesizer IC divides the
12.8 MHz signal down to the 5 or 6.25 kHz signal. (The
KPC-300/400 PC Programming Software will only permit
synthesis of transmit or receive frequencies that are integer
multiples of 5 or 6.25 kHz. Other frequencies cannot be input
into the radio’s personality. The synthesizer’s default phase
lock frequency is 5.0 kHz. If the frequency to be synthesized
is not an integer multiple of 5 kHz, the synthesizer’s phase
lock frequency will be 6.25 kHz.) An unlock detector is used
to prevent transmission when the frequency synthesizer is
unlocked.
Audio modulation from the Audio Signal Processor
(ASP) IC U401 is applied to the VCO modulation input via
amplifier U402 and the TCXO modulation input via ampli-
fier U402. The gain of U402 is adjusted dependent upon the
channel spacing mode of the radio. In the 25 kHz channel
space mode, U418 is open-circuited, removing R453 from
being in parallel with R411. In the 12.5 kHz channel space
mode, U418 is short-circuited, placing R453 in parallel with
R411 and reducing the transmitter audio gain by a factor of
two. (This establishes the 5 kHz maximum frequency devia-
tion for 25 kHz channel spacing and the 2.5 kHz maximum
frequency deviation for 12.5 kHz channel spacing.) VR403
and VR402 are adjustable to provide a constant modulation
flatness for voice audio and Channel Guard (CG) and Digital
Channel Guard (DCG) sub-audible modulation.
MOSFET transistor Q316 is turned on during the transmit
mode to change the loop gain in order to get lower modula-
tion frequency response. A ripple filter, consisting of Q312,
C312 and R331, provides a filtered 4.7 VDC to the VCO to
improve the phase noise characteristic of the receiver local
injection signal for enhanced receiver performance for adja-
cent channel selectivity, intermodulation and FM hum and
noise.
Audio Logic
The audio logic section consists of CPU U404, Audio
Signal Processor (ASP) IC U401, EEPROM U406 and asso-
ciated components. The CPU controls all radio operations.
The EEPROM contains the personality data and the align-
ment data.
CPU
The CPU contains the LCD controller, LED controls, 32k
bytes of ROM, 1k byte of RAM, an 8-channel A/D converter
and a 2-channel D/A converter. The CPU generates DTMF
tones, alert tones, beep tones, GE-STAR (ANI) codes and
Digital Channel Guard (DCG) encode codewords. The DCG
encode codeword from the CPU is applied to a low pass filter
in the ASP IC U401 and summed with the voice signal at
U402. Received DCG codewords and Type 99 tones from the
ASP U401 are supplied and decoded by the CPU.
AUDIO SIGNAL PROCESSOR U401
The ASP IC U401 contains the CG encoder and decoder,
pre-emphasis audio shaping filters, de-emphasis audio shap-
ing filters, limiter, post-limiter filter (i.e., splatter filter) and
various Switched Capacitor Filters (SCF). U401 generates
CG tones controlled by the CPU. CG and DCG sub-audible
modulation signals are summed with the voice audio signal
at op-amp U402 and supplied to the VCO and TCXO modu-
lation inputs.
The demodulated audio signal from IF IC U101 can
provide voice signal information, CG tones, DCG codewords
and Type 99 two-tone sequential information. CG tones are
filtered by a tone filter and decoded in the ASP. DCG code-
words are filtered by the tone filter and input to multiplexer
U417. Type 99 tones are filtered by a bandpass filter and also
input to U417. Multiplexer U417 selects either the DCG or
Type 99 signals, outputs the signal to a comparator to
“square” the signal to a TTL level digital waveform and then,
sends the digitized signal to the CPU for detection.
Before the transmit voice audio signal is inputted to the
ASP, it can be optionally mixed with DTMF or GE-STAR
(ANI) encode signals. These baseband signals are pre-em-
phasized, bandpass filtered, hard limited, run through a post-
limiter filter (splatter filter) and then summed at op-amp
U402 with CG tones or DCG codewords.
CLOCK SHIFT
The CPU uses a nominal 7.3728 MHz clock frequency,
which is divided down to 3.6864 MHz to become the clock
frequency input provided to the ASP IC U401. Harmonics of
this clock frequency can potentially interfere with the per-
formance of the transmitter and receiver, producing self-qui-
eting “beat” notes at specific receiver frequencies or
producing an audio whine at specific transmitter frequencies.
A clock shift can be programmed for each channel’s receive
and/or transmit frequency to move the potentially interfering
harmonics of the microprocessor clock frequency. The mi-
croprocessor clock frequency is shifted more than +100 ppm,
effectively moving potentially interfering clock harmonics
off-channel.
AE/LZB 119 1874 R1A
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