10. PRECAUTIONS
S1C33 Family In-Circuit Debugger
EPSON 37
S5U1C33001H1400 Manual (Rev. 0.20)
10.2 Differences from the actual IC
The S5U1C33001H is different from the actual IC in the way specified below. If this difference is not
taken into consideration in an application, the program may not operate normally in the actual IC.
10.2.1 Register
initialization
When the actual IC is powered on, the contents of all registers except the PC (program
counter) and PSR (processor status register) are indeterminate and retain the immediately
preceding values after a reset, whereas in the S5U1C33001H all registers are initialized
when the debugger on the host computer is invoked.
At this time, the registers are initialized with the following data:
(For all cores)
PSR (processor status register):
0x00000000
AHR, ALR (arithmetic operation high/low registers):
0xAAAAAAAA
R0 through R15 (general-purpose registers):
0xAAAAAAAA
(For C33 STD, Mini and PE cores)
PC
(program
counter):
0x00C00000
(Note)
SP
(stack
pointer): 0x0AAAAAA8
(For C33 ADV core)
PC
(program
counter):
0x20000000
(Note)
LCO (loop count register):
0x00000000
LSA (loop start address register):
0x00000000
LEA (loop end address register):
0x00000000
SOR (shift out register):
0x00000000
TTBR (trap table base register):
0x20000000
DP
(data
pointer): 0x00000000
USP
(user
stack
pointer):
0x00000000
SSP (supervisor stack pointer):
0x00000000
For this reason, never create a program that depends on the initialized value. However, for
reset input from the target system when the target program is being executed, the
S5U1C33001H retains the immediately preceding values, as with the actual IC. For details
on each register, refer to the C33 Core Manual.
Note: The PC initial value is decided according to the setting value of the trap table base
register (boot address). Refer to the “S1C33xxx Technical Manual” for details on the
trap table base register (TTBR).
