10. PRECAUTIONS
S1C33 Family In-Circuit Debugger
EPSON 35
S5U1C33001H1400 Manual (Rev. 0.20)
10.1.11 Reset sequence
The sequence from when the S5U1C33001H is powered on until the execution of the target
program is executed is entirely different from that of the actual S1C33xxx chip.
However, a sequence for the reset requests input from the target system while the target
program is being executed is the same as that for the actual S1C33xxx chip.
Regarding the reset sequence in the actual S1C33xxx chip, refer to the “S1C33xxx
Technical Manual”.
10.1.12 Break functions when a reset request is accepted
If a cold reset request from the target system is accepted when the target system is being
executed, the hardware PC break and data break functions are disabled until execution of
the target program is suspended.
In the case of a hot reset request, there is no such restriction.
10.1.13 I/O memory dump by the S5U1C33001H
Note that some S1C33xxx peripheral circuits may change the control register status due to
their specifications when the I/O memory is read using the memory dump function of the
S5U1C33001H or when the target program execution is suspended.
For details on the memory dump function, refer to the “Debugger” section in the
“S5U1C33001C Manual (C Compiler Package for S1C33 Family)”.
10.1.14 Parameter file
Make sure the parameter file for the S5U1C33001H is set correctly according to the
specifications of the target system.
For details on the parameter file, refer to the “Debugger” section in the “S5U1C33001C
Manual (C Compiler Package for S1C33 Family)”.
