Epson S1C62 Family, Reference Manual

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ICE CONTROL SOFTWARE ICS62XX
VIII-10
EPSON
S1C62 FAMILY
DEVELOPMENT TOOL REFERENCE MANUAL
2.3 S5U1C62000H Operation and Functions
ICE operations, details on functions and emulation limitations are discussed in this section.
2.3.1
Operating features
Figure 2.3.1.1 shows a block
diagram of ICE functions.
The ICE has a built-in control
processor which processes ICE
commands.
Emulation consists of executing
and terminating functions of the
evaluation boardCPU and is
controlled via the emulation
control portion. The evaluation
board CPU is halted unless the
run (G command) or single step
(T command) operations are
invoked. In this condition the
emulation lamp on the ICE display is OFF and the HALT lamp is ON to indicate the set-up mode. Thus, the
A command, etc., are executed during the set-up mode.
The emulation program memory is set-up by instructions which activate the evaluation board CPU.
In the set-up mode, such operations as loading from the ROM sockets by the ICE control processor and
program setting by the host processor are executed.
Similarly, the evaluation board CPU data RAM is allocated to the emulation data memory.
The history control portion records the execution bus cycles of the evaluation board CPU and consists of a
8192 word
×
88 bit memory. The large memory capacity allows evaluation board CPU register values to be
recorded in real time. The history is written in target run mode, and is analyzed by the ICE control
processor in the set-up mode.
The break control portion has the functions which check the evaluation board CPU bus condition whether
it is at a break point or not, and will stop the execution at the break point. Breaking at CPU register values
is also possible in real time. The ICE control processor monitors the evaluation board CPU on the target
monitor during target run mode. Results are displayed as on-the-fly information.
2.3.2
Break mode and break function
Breaks are supported in many modes.
(1) Break enable mode:
Makes the break function valid. Actions during break are decided according to the mode setting of
break-trace/stop.
(2) Break disable mode:
Makes the break function invalid. ICE SYNC pin pulse output mode which does not terminate the G
command when in break condition. This function can be used as an oscilloscope synchronous signal to
measure the target circuit timing using the pulse as a reference.
(3) Break trace mode:
Temporarily stops the target run during break condition, and quickly restarts the program after
displaying the CPU register and execution time. Effective for viewing the program operation timing,
but not in true real time.
(4) Break stop mode:
A mode to break programs when they are consistent with break conditions.
RS-232C host
interface
ICE firmware
ROM sockets (H, L)
History control portion
Emulation control portion
Evaluation board
interface
To the evaluation board
ICE control
processor
Target monitor portion
Break control portion
Emulation program memory
Emulation data memory
Fig. 2.3.1.1 Block diagram of ICE functions