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Epson S1C17F13, Technical Manual

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4  MEMORY AND BUS

S1C17F13 TeChniCal Manual

 

Seiko epson Corporation 

4-3

(Rev. 1.0)

Flash Security Function

4.3.3  

This IC provides a security function to protect the internal Flash memory from unauthorized reading and tampering 
by using the debugger through ICDmini. Figure 4.3.3.1 shows a Flash security function setting flow.

Development environment

GNU17 IDE

Factory shipment inspection 

process

User

EPSON

file

.PA

Mask data file

Specify the unprotecting password.
(6–12 alphanumeric characters (A–Z, a–z, 0–9))

ROM data and password are recorded.

Programming with 

ROM data and password 

IC with protected Flash

Shipment

Submission

3.3.1  Shipment of IC with ROM Data Programmed and Flash Security Function Setting Flow

Figure 4.

The following shows the status of the IC with protected Flash:
•  The Flash memory data is undefined if it is read from the debugger.
•  An error occurs if an attempt is made to program the Flash memory through ICDmini.

However, the Flash security function can be disabled by entering the unprotecting password predefined to GNU17 
IDE (the security function will take effect again after a reset). For setting the password, refer to the “(S1C17 Family 
C Compiler Package) S5U1C17001C Manual.”

note

:  Disable the Flash security function before debugging an IC with protected Flash via ICDmini. The 

debugging functions may not run normally if the Flash security function is enabled.

RAM1

4.4  

RAM1 can be used to execute the instruction codes copied from another memory as well as storing variables or 
other data. This allows higher speed processing and lower power consumption than Flash memory. RAM1 can only 
be accessed by the CPU.

note

:  The 64 bytes at the end of RAM1 is reserved as the debug RAM area. When using the debug 

functions under application development, do not access this area from the application program.

 

This area can be used for applications of mass-produced devices that do not need debugging.

The  RAM1  size  used  by  the  application  can  be  configured  to  equal  or  less  than  the  implemented  size  using  the 
MSCIRAMSZ.IRAMSZ[2:0] bits. For example, this function can be used to prevent creating programs that seek 
to access areas outside the RAM area of the target model when developing an application for a model in which the 
RAM size is smaller than this IC. After the limitation is applied, accessing an address outside the RAM1 area results 
in the same operation (undefined value is read out) as when a reserved area is accessed.

RAM2

4.5  

The embedded RAM2 is used to store display data for the EPD. RAM2 allows the EPD timing controller to read 
data as well as accesses from the CPU.
The entire RAM2 area or the area unused for display data can be used as a general-purpose RAM. 

Peripheral Circuit Control Registers

4.6  

The  control  registers  for  the  peripheral  circuits  are  located  in  the  8K-byte  area  beginning  with  address  0x4000. 
Table 4.6.1 shows the control register map. For details of each control register, refer to “List of Peripheral Circuit 
Registers” in the Appendix or “Control Registers” in each peripheral circuit chapter.

Summary of Contents for S1C17F13

Page 1: ...Rev 1 0 CMOS 16 BIT SINGLE CHIP MICROCONTROLLER S1C17F13 Technical Manual ...

Page 2: ... any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party When exporting the products or technology described in this material you should comply with the applicable export control laws and regulations and follow the pr...

Page 3: ...l number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler package Sx Middleware package Yx Writer software Corresponding model numbe...

Page 4: ...H1 or S0 For more information on the reset groups refer to Initialization Conditions Reset Groups in the Power Supply Reset and Clocks chapter R W R Read only bit W Write only bit WP Write only bit with a write protection using the MSCPROT PROT 15 0 bits R W Read write bit R WP Read write bit with a write protection using the MSCPROT PROT 15 0 bits Control bit read write values This manual describ...

Page 5: ... 2 2 3 Reset Sources 2 3 2 2 4 Initialization Conditions Reset Groups 2 4 2 3 Clock Generator CLG 2 5 2 3 1 Overview 2 5 2 3 2 Input Output Pins 2 6 2 3 3 Clock Sources 2 6 2 3 4 Operations 2 8 2 4 Operating Mode 2 11 2 4 1 Initial Boot Sequence 2 11 2 4 2 Transition between Operating Modes 2 11 2 5 Interrupts 2 12 2 6 Control Registers 2 13 PWG VD1 Regulator Control Register 2 13 CLG System Clock...

Page 6: ... 8 5 Interrupt Controller ITC 5 1 5 1 Overview 5 1 5 2 Vector Table 5 1 5 2 1 Vector Table Base Address TTBR 5 3 5 3 Initialization 5 3 5 4 Maskable Interrupt Control and Operations 5 3 5 4 1 Peripheral Circuit Interrupt Control 5 3 5 4 2 ITC Interrupt Request Processing 5 4 5 4 3 Conditions to Accept Interrupt Requests by the CPU 5 4 5 5 NMI 5 4 5 6 Software Interrupts 5 4 5 7 Interrupt Processin...

Page 7: ...3 Port Group 6 13 6 7 5 P4 Port Group 6 14 6 7 6 Pd Port Group 6 15 6 7 7 Common Registers between Port Groups 6 15 7 Watchdog Timer WDT 7 1 7 1 Overview 7 1 7 2 Clock Settings 7 1 7 2 1 WDT Operating Clock 7 1 7 2 2 Clock Supply in DEBUG Mode 7 2 7 3 Operations 7 2 7 3 1 WDT Control 7 2 7 3 2 Operations in HALT and SLEEP Modes 7 2 7 4 Control Registers 7 3 WDT Clock Control Register 7 3 WDT Contr...

Page 8: ...nter Data Register 9 6 T16 Ch n Interrupt Flag Register 9 6 T16 Ch n Interrupt Enable Register 9 7 10 UART UART 10 1 10 1 Overview 10 1 10 2 Input Output Pins and External Connections 10 2 10 2 1 List of Input Output Pins 10 2 10 2 2 External Connections 10 2 10 2 3 Input Pin Pull Up Function 10 2 10 2 4 Output Pin Open Drain Output Function 10 2 10 3 Clock Settings 10 2 10 3 1 UART Operating Cloc...

Page 9: ...ransfer in Master Mode 11 8 11 5 5 Data Transfer in Slave Mode 11 8 11 5 6 Terminating Data Transfer in Slave Mode 11 10 11 6 Interrupts 11 10 11 7 Control Registers 11 11 SPI Ch n Mode Register 11 11 SPI Ch n Control Register 11 11 SPI Ch n Transmit Data Register 11 12 SPI Ch n Receive Data Register 11 12 SPI Ch n Interrupt Flag Register 11 12 SPI Ch n Interrupt Enable Register 11 13 12 I2C I2C 1...

Page 10: ... Register 13 4 14 Real Time Clock RTC 14 1 14 1 Overview 14 1 14 2 Clock Settings 14 1 14 3 RTC Counters 14 1 14 4 Operations 14 3 14 4 1 Time Setting 14 3 14 4 2 Time Read 14 4 14 5 Interrupts 14 4 14 6 Control Registers 14 5 RTC Control Register 14 5 RTC Interrupt Enable Register 14 6 RTC Interrupt Flag Register 14 6 RTC Minute Second Register 14 7 RTC Hour Register 14 7 15 Theoretical Regulatio...

Page 11: ... 2 17 2 3 Pin Pull Up Function 17 2 17 3 Clock Settings 17 2 17 3 1 PIO Operating Clock 17 2 17 3 2 Clock Supply in SLEEP Mode 17 2 17 3 3 Clock Supply in DEBUG Mode 17 2 17 4 Operations 17 2 17 4 1 Initialization 17 2 17 4 2 Operations in SRAM Mode 17 3 17 4 3 Operations in GPIO Mode 17 4 17 5 Control Registers 17 5 PIO Clock Control Register 17 5 PIO Mode Register 17 5 PIO Control Register 17 6 ...

Page 12: ... 20 3 Operations 20 2 20 3 1 Initialization 20 2 20 3 2 Comparison Time Setting 20 2 20 3 3 Temperature Detection 20 3 20 4 Interrupt 20 5 20 5 Control Registers 20 5 TEM Clock Control Register 20 5 TEM Timing Register 20 5 TEM Control Register 20 6 TEM Conversion Result Register 20 6 TEM Interrupt Flag and Status Register 20 6 TEM Interrupt Enable Register 20 7 21 Multiplier Divider COPRO 21 1 21...

Page 13: ...ler FLASHC AP A 5 0x4200 0x42e2 I O Ports PPORT AP A 5 0x4380 0x438e UART UART AP A 8 0x43a0 0x43ac 16 bit Timer T16 Ch 1 AP A 9 0x43b0 0x43ba SPI SPI Ch 0 AP A 10 0x43c0 0x43d2 I2C I2C AP A 10 0x5000 0x500e 16 bit PWM Timer T16A3 Ch 0 AP A 11 0x5020 0x502e 16 bit PWM Timer T16A3 Ch 1 AP A 12 0x5180 0x5186 Clock Timer CT AP A 13 0x5260 0x526c 16 bit Timer T16 Ch 2 AP A 14 0x5270 0x527a SPI SPI Ch ...

Page 14: ...ating frequency 20 MHz max OSC3B internal high speed oscillator circuit boot clock source 20 16 12 8 MHz typ selectable via software OSC1B internal low speed oscillator circuit 32 kHz typ OSC3A high speed oscillator circuit 20 MHz max crystal or ceramic oscillator circuit OSC1A low speed oscillator circuit 32 768 kHz typ crystal oscillator circuit EXOSC clock input 20 MHz max square or sine wave i...

Page 15: ...VDD 1 45 V typ is detected Key entry reset Reset when the P00 to P01 P02 P03 keys are pressed simultaneously can be en abled disabled using a register Watchdog timer reset Reset when the watchdog timer overflows can be enabled disabled using a register Supply voltage detector reset Reset when the supply voltage detector detects the set voltage level can be enabled disabled using a register Interru...

Page 16: ... 16 bit internal bus SDA0 SCL0 EXSVD P00 07 P10 17 P20 27 P30 37 P40 41 PD0 D2 Interrupt controller ITC I O port PPORT Watchdog timer WDT Clock timer CT Real time clock RTC Theoretical Regulation TR I2C I2C Temperature detection circuit TEM R F converter RFC Ch 0 1 Supply voltage detector SVD 16 bit timer T16 Ch 0 3 EXCL0 1 TOUTA0 CAPA0 1 TOUTB0 CAPB0 1 SDI0 2 SDO0 2 SPICLK0 2 SPISS0 2 RFIN0 1 REF...

Page 17: ...DD RESET V SS TEST P13 RFIN0 PIOA7 P12 REF0 PIOA6 P11 SENA0 PIOA5 P10 SENB0 PIOA4 IREF_M V OSC VM1 VM2 OSC2 OSC1 OSC4 OSC3 V DD RESET 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name P14 P15 P16 P17 VSS P20 P21 P22 P23 VDD P24 P25 P26 P27 P30 VSS Port function or signal assignment P14 SENB1 PIOD0 P15 SENA1 PIOD1 P16 REF1 PIOD2 P17 RFIN1 PIOD3...

Page 18: ... P37 P40 P41 PD0 PD1 N C PD2 N C N C N C P00 P01 P31 REGMON RFCLKO1 EXSVD P32 TOUTB1 CAPB1 PIOA0 P33 TOUTA1 CAPA1 PIOA1 V DD V SS P34 USIN0 PIOA2 P35 USOUT0 PIOA3 P36 SCL0 PIOD0 P37 SDA0 PIOD1 P40 USIN0 PIOD2 P41 USOUT0 PIOD3 DST2 PD0 DSIO PD1 DCLK PD2 P00 TOUTA0 CAPA0 FOUT P01 TOUTB0 CAPB0 PIOWR VSS VD1 N C P07 P06 P05 P04 P03 P02 VPP C2P C2N C1H C1P C1N VDD VSS VSS VD1 P07 SDO0 PIOA3 P06 SDI0 PI...

Page 19: ...760 0 20 1110 0 1548 6 77 1578 6 850 0 21 1200 0 1548 6 78 1578 6 940 0 Pin Descriptions 1 3 3 Symbol meanings Assigned signal The signal listed at the top of each pin is assigned in the initial state The pin function must be switched via software to assign another signal see the I O Ports chapter I O I Input O Output I O Input output P Power supply A Analog signal Hi Z High impedance state Initia...

Page 20: ...tput P06 P06 I O Hi Z General purpose I O port SDI0 I Synchronous serial interface Ch 0 data input PIOA2 O Parallel interface address output P07 P07 I O Hi Z General purpose I O port SDO0 O Synchronous serial interface Ch 0 data output PIOA3 O Parallel interface address output P10 P10 I O Hi Z General purpose I O port SENB0 A R F converter Ch 0 sensor B oscillation control PIOA4 O Parallel interfa...

Page 21: ...ck monitor output EXSVD A External power supply voltage detection input P32 P32 I O Hi Z General purpose I O port TOUTB1 CAPB1 I O 16 bit PWM timer Ch 1 TOUTB signal output capture B trigger signal input PIOA0 O Parallel interface address output P33 P33 I O Hi Z General purpose I O port TOUTA1 CAPA1 I O 16 bit PWM timer Ch 1 TOUTA signal output capture A trigger signal input PIOA1 O Parallel inter...

Page 22: ...tion constant independent of the VDD voltage level The VD1 regulator supports two operation modes normal mode and economy mode and setting the VD1 regu lator into economy mode at light loads helps achieve low power operations Embedded VOSC regulator The VOSC regulator drives the low speed oscillator circuit in low power consumption and achieves stabilized low speed clock that is used for timers su...

Page 23: ...for OSC1 is active HALT mode when OSC1 only is active RUN mode when OSC1 only is active The VD1 regulator also supports automatic mode in which the hardware detects a light load condition and automati cally switches between normal mode and economy mode Use the VD1 regulator in automatic mode when no special control is required V 2 1 4 OSC Regulator The VOSC regulator generates the operating voltag...

Page 24: ...ration Figure 2 Input Pin 2 2 2 Table 2 2 2 1 shows the SRC pin 2 2 1 SRC Pin Table 2 Pin name I O Initial status Function RESET I I Pull up Reset input The RESET pin is connected to the noise filter that removes pulses not conforming to the requirements An inter nal pull up resistor is connected to the RESET pin so the pin can be left open For the RESET pin characteris tics refer to RESET pin cha...

Page 25: ...more information refer to the Supply Volt age Detector chapter Peripheral circuit software reset Some peripheral circuits provide a control bit for software reset MODEN or SFTRST Setting this bit initial izes the peripheral circuit control bits Note however that the software reset operations depend on the periph eral circuit For more information refer to Control Registers in each peripheral circui...

Page 26: ...ck input circuits to enable disable according to the operating mode RUN or SLEEP mode Provides a flexible system clock switching function at SLEEP mode cancelation The clock sources to be stopped in SLEEP mode can be selected SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources OSC3B OSC3A and EXOSC The oscillator and clock input circuit on off state can be maintained...

Page 27: ... as SYSCLK at booting The OSC3BCLK frequency can be selected using the CLGOSC3B OSC3BFREQ 1 0 bits For more information on the oscillation characteristics refer to OSC3B oscillator circuit characteristics in the Electrical Characteristics chapter OSC3A oscillator circuit The OSC3A oscillator circuit is a high speed oscillator circuit that uses a crystal or ceramic resonator Figure 2 3 3 2 shows th...

Page 28: ...onfiguration Figure 2 OSC1A oscillator circuit The OSC1A oscillator circuit is a high precision and low power oscillator circuit that uses a 32 768 kHz crystal resonator A crystal resonator X tal1 should be connected between the OSC1 and OSC2 pins Ad ditionally two capacitors CG1 and CD1 should be connected between the OSC1 OSC2 pins and VSS For the recommended parts and the oscillation characteri...

Page 29: ...stabilized immediately after the oscillation starts or not monitor the oscillation clock using the FOUT output function The oscillation stabilization waiting time for the OSC3B oscillator circuit is fixed at 128 OSC3BCLK clocks When the oscillation stabilization waiting operation has completed the oscillator circuit sets the oscillation sta bilization waiting completion flag and starts clock suppl...

Page 30: ...according to the resonator used CLGOSC1 OSC1WT 1 0 bits Set oscillation stabilization waiting time Set the CLGOSC1 OSC1SEL bit to 0 Select OSC1A 5 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection 6 Write 1 to the CLGOSC OSC1EN bit Start oscillation 7 OSC1CLK can be used if the CLGINTF OSC1STAIF bit 1 after an interrupt occurs The setting value of the CLGOSC1 OSC1...

Page 31: ... WUPSRC 1 0 bits 0x0 SYSCLK CPU operating clock SLEEP mode CPU stop CLK stop Executing the slp instruction Interrupt Wake up OSC1CLK OSC3BCLK Switching to OSC3B that features fast initiation allows high speed processing OSC3BCLK Unstable Oscillation stabilization waiting time OSC3BCLK Unstable CLGSCLK CLKSRC 1 0 0x1 OSC1 CLGSCLK WUPSRC 1 0 0x0 OSC3B CLGSCLK CLKSRC 1 0 0x0 OSC3B CLGSCLK WUPSRC 1 0 ...

Page 32: ...on it suspends program execution and stops operating This state is HALT mode In this mode the clock sources and peripheral circuits keep operating This mode can be set while no software processing is required and it reduces power consumption as compared with RUN mode HALT mode is classified into OSC3B HALT OSC1 HALT OSC3A HALT and EXOSC HALT by the SYS CLK clock source SLEEP mode When the CPU exec...

Page 33: ... 0 0 x 0 C L G S C L K C L K S R C 1 0 0 x 3 C L G S C L K C L K S R C 1 0 0 x 1 C L G S C L K C L K S R C 1 0 0 x 2 4 2 1 Operating Mode to Mode State Transition Diagram Figure 2 Canceling HALT or SLEEP mode The conditions listed below cancel HALT or SLEEP mode and put the CPU into RUN mode Interrupt request from the interrupt controller NMI from the watchdog timer Debug interrupt or address misa...

Page 34: ...PDIV 1 0 0x0 H0 R WP 11 10 0x0 R 9 8 WUPSRC 1 0 0x0 H0 R WP 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R WP 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R WP Bit 15 WUPMD This bit enables the SYSCLK switching function at wake up 1 R WP Enable 0 R WP Disable When the CLGSCLK WUPMD bit 1 setting values of the CLGSCLK WUPSRC 1 0 bits and the CLGSCLK WUPDIV 1 0 bits are loaded to the CLGSCLK CLKSRC 1 0 bits and the CLGSCLK C...

Page 35: ... determine the SYSCLK frequency Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the SYSCLK clock source When a currently stopped clock source is selected it will automatically start oscillating or clock input 6 3 SYSCLK Clock Source and Division Ratio Settings Table 2 CLGSCLK CLKDIV 1 0 bits CLGSCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 OSC3BCLK OSC1CLK OSC3ACLK EXOSCCLK 0x3 Reserved Reserved 1 ...

Page 36: ...circuit CLGOSC OSC1EN bit OSC1 oscillator circuit CLGOSC OSC3BEN bit OSC3B oscillator circuit CLG OSC3B Control Register Register name Bit Bit name Initial Reset R W Remarks CLGOSC3B 15 8 0x00 R 7 2 0x00 R 1 0 OSC3BFREQ 1 0 0x0 H0 R WP Bits 15 2 Reserved Bits 1 0 OSC3BFREQ 1 0 These bits select the OSC3BCLK frequency 6 4 OSC3BCLK Frequency Selection Table 2 CLGOSC3B OSC3BFREQ 1 0 bits OSC3BCLK fre...

Page 37: ...le 2 CLGOSC3A INVN 1 0 bits Inverter gain 0x3 Max 0x2 0x1 0x0 Min Bits 3 2 Reserved Bits 1 0 OSC3AWT 1 0 These bits set the oscillation stabilization waiting time for the OSC3A oscillator circuit 6 7 OSC3A Oscillation Stabilization Waiting Time Setting Table 2 CLGOSC3A OSC3AWT 1 0 bits Oscillation stabilization waiting time 0x3 4 096 clocks 0x2 1 024 clocks 0x1 256 clocks 0x0 Reserved CLG Interrup...

Page 38: ... R W Enable interrupts 0 R W Disable interrupts Each bit corresponds to the clock source as follows CLGINTE OSC3ASTAIE bit OSC3A oscillator circuit CLGINTE OSC1STAIE bit OSC1 oscillator circuit CLGINTE OSC3BSTAIE bit OSC3B oscillator circuit CLG FOUT Control Register Register name Bit Bit name Initial Reset R W Remarks CLGFOUT 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTSRC 1 0 0x0 H0 R W...

Page 39: ...UT output will be stopped in SLEEP HALT mode as SYSCLK is stopped Bit 1 Reserved Bit 0 FOUTEN This bit controls the FOUT clock external output 1 R W Enable external output 0 R W Disable external output Note Since the FOUT signal generated is out of sync with writings to the CLGFOUT FOUTEN bit a glitch may occur when the FOUT output is enabled or disabled ...

Page 40: ...ed up to 24 bits Supports reset NMI address misaligned debug and external interrupts Reads a vector from the vector table and branches to the interrupt handler routine directly Can generate software interrupts with a vector number specified all vector numbers specifiable HALT mode halt instruction and SLEEP mode slp instruction are provided as the standby function Incorporates a debugger with thre...

Page 41: ...reserved for the S1C17 core Do not access this area ex cept when it is required Debugger 3 3 Debugging Functions 3 3 1 The debugger provides the following functions Instruction break A debug interrupt is generated immediately before the set instruction address is executed An instruction break can be set at up to four addresses Single step A debug interrupt is generated after each instruction has b...

Page 42: ...urpose I O ports and are initially set as the debug pins If the debugging function is not used these pins can be switched to general purpose I O port pins For details refer to the I O Ports chapter External Connection 3 3 4 Figure 3 3 4 1 shows a connection example between this IC and ICDmini when performing debugging DCLK DSIO DST2 DCLK DSIO DST2 VDD ICDmini S5U1C17001H S1C17 RDBG 3 4 1 External ...

Page 43: ... Bit 1 PSRZ The value 0 or 1 of the PSR Z zero flag can be read out with this bit Bit 0 PSRN The value 0 or 1 of the PSR N negative flag can be read out with this bit Debug RAM Base Register Register name Bit Bit name Initial Reset R W Remarks DBRAM 31 24 0x00 R 23 0 DBRAM 23 0 1 H0 R 1 Debugging work area start address Bits 31 24 Reserved Bits 23 0 DBRAM 23 0 The start address of the debugging wo...

Page 44: ...ce size 16 bits 0x00 4000 0x00 3fff Reserved 0x00 1000 0x00 17ff 0x00 17c0 Debug RAM area 64 bytes 0x00 17bf RAM area 1 6K bytes Device size 32 bits 0x00 0000 1 RAM area 2 is a shared area for the CPU and EPD timing controller and one wait cycle will be inserted to the CPU access cycle two cycle access if this area is accessed from both simultaneously 1 1 Memory Map Figure 4 Note Be sure to avoid ...

Page 45: ...tes an instruction stored in the internal RAM area and accesses data in the internal RAM area Flash Memory 4 3 The Flash memory is used to store application programs and data Address 0x8000 in the Flash area is defined as the vector table base address by default therefore a vector table must be located beginning from this address For more information on the vector table refer to Vector Table in th...

Page 46: ...he instruction codes copied from another memory as well as storing variables or other data This allows higher speed processing and lower power consumption than Flash memory RAM1 can only be accessed by the CPU Note The 64 bytes at the end of RAM1 is reserved as the debug RAM area When using the debug functions under application development do not access this area from the application program This ...

Page 47: ...etup Register 9 Watchdog timer WDT 0x40a0 WDTCLK WDT Clock Control Register 0x40a2 WDTCTL WDT Control Register Real time clock RTC 0x40c0 RTCCTL RTC Control Register 0x40c2 RTCINTE RTC Interrupt Enable Register 0x40c4 RTCINTF RTC Interrupt Flag Register 0x40c6 RTCMIN RTC Minute Second Register 0x40c8 RTCHUR RTC Hour Register Supply voltage detector SVD 0x4100 SVDCLK SVD Clock Control Register 0x41...

Page 48: ...Receive Data Register 0x438c UA0INTF UART Ch 0 Status and Interrupt Flag Register 0x438e UA0INTE UART Ch 0 Interrupt Enable Register 16 bit timer T16 Ch 1 0x43a0 T16_1CLK T16 Ch 1 Clock Control Register 0x43a2 T16_1MOD T16 Ch 1 Mode Register 0x43a4 T16_1CTL T16 Ch 1 Control Register 0x43a6 T16_1TR T16 Ch 1 Reload Data Register 0x43a8 T16_1TC T16 Ch 1 Counter Data Register 0x43aa T16_1INTF T16 Ch 1...

Page 49: ...3 0x5280 T16_3CLK T16 Ch 3 Clock Control Register 0x5282 T16_3MOD T16 Ch 3 Mode Register 0x5284 T16_3CTL T16 Ch 3 Control Register 0x5286 T16_3TR T16 Ch 3 Reload Data Register 0x5288 T16_3TC T16 Ch 3 Counter Data Register 0x528a T16_3INTF T16 Ch 3 Interrupt Flag Register 0x528c T16_3INTE T16 Ch 3 Interrupt Enable Register SPI SPI Ch 2 0x5290 SPI2MOD SPI Ch 2 Mode Register 0x5292 SPI2CTL SPI Ch 2 C...

Page 50: ...s provided to prevent deadlock that may occur when a system related register is altered by a runaway CPU See Control Registers in each peripheral circuit to identify the registers and bits with write protection Note Once write protection is removed using the MSCPROT PROT 15 0 bits write enabled status is maintained until write protection is applied again After the registers bits required have been...

Page 51: ...8 Reserved Bit 7 XBUSY This bit indicates whether the Flash memory can be accessed or not 1 R Flash memory ready to access 0 R Flash access prohibited The Flash memory can always be accessed during normal operation Bits 6 2 Reserved Bits 1 0 RDWAIT 1 0 These bits set the number of bus access cycles for reading from the Flash memory 7 2 Setting Number of Bus Access Cycles for Flash Read Table 4 FLA...

Page 52: ... Interrupt request NMI ILVx 2 0 Interrupt control circuit ILVy 2 0 Interrupt request Peripheral circuit Peripheral circuit Internal data bus 1 1 ITC Configuration Figure 5 Vector Table 5 2 The vector table contains the vectors to the interrupt handler routines handler routine start address that will be read by the CPU to execute the handler when an interrupt occurs Table 5 2 1 shows the vector tab...

Page 53: ...ow 11 0x0b TTBR 0x2c SPI Ch 0 interrupt End of transmission Receive buffer full Transmit buffer empty 12 0x0c TTBR 0x30 I2 C interrupt End of data transfer General call address reception NACK reception STOP condition START condition Error detection Receive buffer full Transmit buffer empty 13 0x0d TTBR 0x34 Clock timer interrupt 32 Hz 8 Hz 2 Hz 1 Hz 14 0x0e TTBR 0x38 16 bit timer Ch 2 interrupt Un...

Page 54: ...ion to set the CPU into interrupt disabled state 2 If the vector table start address is different from the default address set it to the MSCTTBRL and MSCTTBRH registers after removing system protection by writing 0x0096 to the MSCPROT PROT 15 0 bits Then write a value other than 0x0096 to the MSCPROT PROT 15 0 bits to set system protection 3 Set the interrupt enable bit of the peripheral circuit t...

Page 55: ...occurs while the ITC is outputting an interrupt request signal to the CPU before being accepted by the CPU the ITC alters the vector number and interrupt level signals to the setting in formation on the more recent interrupt The previously occurring interrupt is held The held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software...

Page 56: ...r routines using the reti instruction returns the PSR to the state before the interrupt occurred The program resumes processing following the instruction being executed at the time the interrupt occurred Note At wake up from HALT or SLEEP mode the CPU jumps to the interrupt handler routine after executing one instruction To execute the interrupt handler routine immediately after wake up place the ...

Page 57: ...SPI_0 7 3 0x00 R 2 0 ILV6 2 0 0x0 H0 R W 16 bit timer Ch 1 interrupt ILVT16_1 ITCLV4 ITC Interrupt Level Setup Register 4 15 11 0x00 R 10 8 ILV9 2 0 0x0 H0 R W Clock timer interrupt ILVCT 7 3 0x00 R 2 0 ILV8 2 0 0x0 H0 R W I2C interrupt ILVI2C_0 ITCLV5 ITC Interrupt Level Setup Register 5 15 11 0x00 R 10 8 ILV11 2 0 0x0 H0 R W SPI Ch 1 interrupt ILVSPI_1 7 3 0x00 R 2 0 ILV10 2 0 0x0 H0 R W 16 bit ...

Page 58: ...t number y 0 1 2 7 Figure 6 1 1 shows the configuration of PPORT Port configuration in this IC Port groups included P0 7 0 P1 7 0 P2 7 0 P3 7 0 P4 1 0 Pd 2 0 Ports with general purpose I O function GPIO P0 7 0 P1 7 0 P2 7 0 P3 7 0 P4 1 0 Pd 2 0 Pd2 output only Ports with interrupt function P0 7 0 P1 7 0 Ports for debug function Pd 2 0 Key entry reset function Supported P0 3 0 Pxy PPORT Pxy Pxy Per...

Page 59: ...Type I O Cell 6 2 2 The over voltage tolerant fail safe type I O cell allows interfacing without passing unnecessary current even if a voltage exceeding VDD is applied to the port Also unnecessary current is consumed when the port is externally bi ased without supplying VDD However be sure to avoid applying a voltage exceeding the recommended maximum operating power supply voltage to the port Pull...

Page 60: ...LK_PPORT must be configured so that it will keep suppling by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_PPORT clock source If the CLGOSC xxxxSLPC bit for the CLK_PPORT clock source is 1 the CLK_PPORT clock source is deacti vated during SLEEP mode and it disables the chattering filter function regardless of the PxCHATEN PxCHATENy bit setting chattering filter enabled disabled Clock Supply in ...

Page 61: ...ose input port only for the ports with GPIO function When using the Pxy port pin as a general purpose input pin perform the following software initial settings 1 Write 0 to the PxINTCTL PxIEy bit Disable interrupt 2 When using the chattering filter configure the PPORT operating clock see PPORT Operating Clock and set the PxCHATEN PxCHATENy bit to 1 When the chattering filter is not used set the Px...

Page 62: ...a chattering filter function and it can be controlled in each port This function is enabled by setting the PxCHATEN PxCHATENy bit to 1 The input sampling time to remove chattering is determined by the CLK_PPORT frequency configured using the PCLK register in common to all ports The chattering filter removes pulses with a shorter width than the input sampling time 3 Input sampling time second Eq 6 ...

Page 63: ...r Interrupt check in port group unit When interrupts are enabled in two or more port groups check the PINTFGRP PxINT bit in the interrupt han dler first It helps minimize the handler codes for finding the port that has generated an interrupt If this bit is set to 1 an interrupt has occurred in the port group Next check the PxINTF PxIFy bit set to 1 in the port group to determine the port that has ...

Page 64: ...able disable the GPIO port output 1 R W Enable Data is output from the port pin 0 R W Disable The port is placed into Hi Z These bits do not affect the output control when the port is used as a peripheral I O function Px Port Pull up down Control Register Register name Bit Bit name Initial Reset R W Remarks PxRCTL 15 8 PxPDPU 7 0 0x00 H0 R W 7 0 PxREN 7 0 0x00 H0 R W 1 This register is effective w...

Page 65: ...E 7 0 These bits select the input signal edge to generate a port input interrupt 1 R W An interrupt will occur at a falling edge 0 R W An interrupt will occur at a rising edge Bits 7 0 PxIE 7 0 These bits enable port input interrupts 1 R W Enable interrupts 0 R W Disable interrupts Note To prevent generating unnecessary interrupts clear the corresponding interrupt flag before en abling interrupts ...

Page 66: ... 6 1 Selecting Peripheral I O Function Table 6 PxFNCSEL PxyMUX 1 0 bits Peripheral I O function 0x3 Function 3 0x2 Function 2 0x1 Function 1 0x0 Function 0 This selection takes effect when the PxMODSEL PxSELy bit 1 P Port Clock Control Register Register name Bit Bit name Initial Reset R W Remarks PCLK 15 9 0x00 R 8 DBRUN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 KRSTCFG 1 0 0x0 H0 R WP 1 0 CLKSRC 1...

Page 67: ...6 1 64 0x5 1 32 0x4 1 16 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source P Port Interrupt Flag Group Register Register name Bit Bit name Initial Reset R W Remarks PINTFGRP 15 13 0x0 R 12 PcINT 0 H0 R 11 PbINT 0 H0 R 10 PaINT 0 H0 R 9 P9INT 0 H0 R 8 P8INT 0 H0 R 7 P7INT 0 H0 R 6 P6INT 0 H0 R 5 P5IN...

Page 68: ...INTCTL P0 Port Interrupt Control Register 15 8 P0EDGE 7 0 0x00 H0 R W 7 0 P0IE 7 0 0x00 H0 R W P0CHATEN P0 Port Chattering Filter Enable Register 15 8 0x00 R 7 0 P0CHATEN 7 0 0x00 H0 R W P0MODSEL P0 Port Mode Select Register 15 8 0x00 R 7 0 P0SEL 7 0 0x00 H0 R W P0FNCSEL P0 Port Function Select Register 15 14 P07MUX 1 0 0x0 H0 R W Valid settings 0x0 0x1 13 12 P06MUX 1 0 0x0 H0 R W 11 10 P05MUX 1 0...

Page 69: ...R W P1FNCSEL P1 Port Function Select Register 15 14 P17MUX 1 0 0x0 H0 R W Valid settings 0x0 0x1 13 12 P16MUX 1 0 0x0 H0 R W 11 10 P15MUX 1 0 0x0 H0 R W 9 8 P14MUX 1 0 0x0 H0 R W 7 6 P13MUX 1 0 0x0 H0 R W 5 4 P12MUX 1 0 0x0 H0 R W 3 2 P11MUX 1 0 0x0 H0 R W 1 0 P10MUX 1 0 0x0 H0 R W 7 2 2 P1 Port Group Function Assignment Table 6 Port name P1SELy 0 P1SELy 1 GPIO P1yMUX 0x0 Function 0 P1yMUX 0x1 Fun...

Page 70: ... P2yMUX 0x0 Function 0 P2yMUX 0x1 Function 1 P2yMUX 0x2 Function 2 P2yMUX 0x3 Function 3 Peripheral Pin Peripheral Pin Peripheral Pin Peripheral Pin P20 P20 SPI Ch 1 SDO1 PIO PIOD4 P21 P21 SPI Ch 1 SDI1 PIO PIOD5 P22 P22 SPI Ch 1 SPICLK1 PIO PIOD6 P23 P23 SPI Ch 1 SPISS1 PIO PIOD7 P24 P24 SPI Ch 2 SPISS2 P25 P25 SPI Ch 2 SPICLK2 P26 P26 SPI Ch 2 SDI2 P27 P27 SPI Ch 2 SDO2 P3 Port Group 6 7 4 The P...

Page 71: ...T0 PIO PIOA3 P36 P36 I2C SCL0 PIO PIOD0 P37 P37 I2C SDA0 PIO PIOD1 P4 Port Group 6 7 5 The P4 port group supports the GPIO function 7 5 1 Control Registers for P4 Port Group Table 6 Register name Bit Bit name Initial Reset R W Remarks P4DAT P4 Port Data Register 15 10 0x00 R 9 8 P4OUT 1 0 0x0 H0 R W 7 2 0x00 R 1 0 P4IN 1 0 x H0 R P4IOEN P4 Port Enable Register 15 10 0x00 R 9 8 P4IEN 1 0 0x0 H0 R W...

Page 72: ...7 3 0x00 R 2 reserved 0 H0 R W 1 0 PDREN 1 0 0x0 H0 R W PDINTF PDINTCTL PDCHATEN 15 0 0x0000 R PDMODSEL Pd Port Mode Select Register 15 8 0x00 R 7 3 0x00 R 2 0 PDSEL 2 0 0x7 H0 R W PDFNCSEL Pd Port Function Select Register 15 8 0x00 R 7 6 0x0 R 5 4 PD2MUX 1 0 0x0 H0 R W Valid settings 0x0 3 2 PD1MUX 1 0 0x0 H0 R W 1 0 PD0MUX 1 0 0x0 H0 R W 7 6 2 Pd Port Group Function Assignment Table 6 Port name ...

Page 73: ... 7 2 1 When using WDT the WDT operating clock CLK_WDT must be supplied to WDT from the clock generator The CLK_WDT supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following...

Page 74: ... WDTCTL WDTCNTRST bit Reset WDT counter 3 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection A location should be provided for periodically processing this routine Process this routine within the tWDT cycle After resetting WDT starts counting with a new NMI reset generation cycle If WDT is not reset within the tWDT cycle for any reason the CPU is switched to interr...

Page 75: ... Bits 1 0 CLKSRC 1 0 These bits select the clock source of WDT 4 1 Clock Source and Division Ratio Settings Table 7 WDTCLK CLKDIV 1 0 bits WDTCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 OSC3B OSC1 OSC3A EXOSC 0x3 1 65 536 1 128 1 65 536 1 1 0x2 1 32 768 1 32 768 0x1 1 16 384 1 16 384 0x0 1 8 192 1 8 192 Note The oscillation circuits external input that are not supported in this IC cannot be selected as th...

Page 76: ...n firm that WDT was the source of the NMI The STATNMI set to 1 is cleared to 0 by resetting WDT Bits 7 5 Reserved Bit 4 WDTCNTRST This bit resets WDT 1 WP Reset 0 WP Ignored 0 R Always 0 when being read Bits 3 0 WDTRUN 3 0 These bits control WDT to run and stop 0xa R WP Stop Values other than 0xa R WP Run Always 0x0 is read if a value other than 0xa is written Since an NMI or reset may be generate...

Page 77: ...nterrupt or a reset when low power supply voltage is de tected Interrupt 1 system Low power supply voltage detection interrupt Supports intermittent operations Three detection cycles are selectable Low power supply voltage detection count function to generate an inter rupt reset when low power supply voltage is successively detected the number of times specified Continuous operation is also possib...

Page 78: ...g clock CLK_SVD must be supplied to SVD from the clock generator The CLK_SVD supply should be controlled as in the procedure shown below 1 Write 0x0096 to the MSCPROT PROT 15 0 bits Remove system protection 2 Enable the clock source in the clock generator if it is stopped refer to Clock Generator in the Power Supply Reset and Clocks chapter 3 Set the following SVDCLK register bits SVDCLK CLKSRC 1 ...

Page 79: ...g bits when using the interrupt Write 1 to the SVDINTF SVDIF bit Clear interrupt flag Set the SVDINTE SDVIE bit to 1 Enable SVD interrupt 5 Set the SVDCTL MODEN bit to 1 Enable SVD detection 6 Write a value other than 0x0096 to the MSCPROT PROT 15 0 bits Set system protection Terminating detection Follow the procedure shown below to stop SVD operation 1 Write 0x0096 to the MSCPROT PROT 15 0 bits R...

Page 80: ...ified by the SVDCTL SVDSC 1 0 bits 1 When the SVDCTL SVDMD 1 0 bits 0x0 continuous operation mode VSVD VSVD VDD SVDCTL MODEN SVD operating status SVDINTF SVDDT Low power supply voltage detection interrupt DET 2 When the SVDCTL SVDMD 1 0 bits 0x0 intermittent operation mode VSVD Level set using the SVDCTL SVDC 4 0 bits Voltage detection masking time Voltage detection operation DET VSVD VSVD VDD SVD...

Page 81: ... is can celed After that SVD resumes operating in the operation mode set previously via the initialization routine During reset state the SVD control bits are set as shown in Table 8 5 2 1 5 2 1 SVD Control Bits During Reset State Table 8 Control register Control bit Setting SVDCLK DBRUN Reset to the initial values CLKDIV 2 0 CLKSRC 1 0 SVDCTL VDSEL The set value is retained SVDSC 1 0 Cleared to 0...

Page 82: ...detected by SVD 1 R WP Voltage applied to the EXSVD pin 0 R WP VDD Bits 14 13 SVDSC 1 0 These bits set the condition to generate an interrupt reset number of successive low voltage detec tions in intermittent operation mode SVDCTL SVDMD 1 0 bits 0x1 to 0x3 6 2 Interrupt Reset Generating Condition in Intermittent Operation Mode Table 8 SVDCTL SVDSC 1 0 bits Interrupt reset generating condition 0x3 ...

Page 83: ...t without subsequent operations being performed Notes Writing 0 to the SVDCTL MODEN bit resets the SVD hardware However the register values set and the interrupt flag are not cleared The SVDCTL MODEN bit is actually set to 0 after this processing has finished If 1 is written to the SVDCTL MODEN bit continuously without waiting for the bit being read as 0 at this time writing 0 may be ignored and a...

Page 84: ...e Initial Reset R W Remarks SVDINTE 15 8 0x00 R 7 1 0x00 R 0 SVDIE 0 H0 R W Bits 15 1 Reserved Bit 0 SVDIE This bit enables low power supply voltage detection interrupts 1 R W Enable interrupts 0 R W Disable interrupts Notes If the SVDCTL SVDRE 3 0 bits are set to 0xa no low power supply voltage detection in terrupt will occur as a reset is issued at the same timing as an interrupt To prevent gene...

Page 85: ... 3 SPI Ch 2 master clock Outputs the counter underflow signal T16 Ch n To interrupt controller To peripheral circuit Underflow PRESET Timer control circuit Interrupt control circuit Chattering filter PRUN TRMD CLKSRC 1 0 CLKDIV 3 0 Clock generator I O port UFIE UFIF DBRUN MODEN CLK_T16_n EXCLm Timer counter TC 15 0 Reload register TR 15 0 Internal data bus 1 1 Configuration of a T16 Channel Figure...

Page 86: ...during DEBUG mode should be controlled using the T16_nCLK DBRUN bit The CLK_T16_n supply to T16 Ch n is suspended when the CPU enters DEBUG mode if the T16_nCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_T16_n supply resumes Although T16 Ch n stops operat ing when the CLK_T16_n supply is suspended the counter and registers retain the status before DEBUG mode was entered If the T16_nC...

Page 87: ...g clock frequency Hz Operations in Repeat Mode 9 4 3 T16 Ch n enters repeat mode by setting T16_nMOD TRMD bit to 0 In repeat mode the count operation starts by writing 1 to the T16_nCTL PRUN bit and continues until 0 is written A counter underflow presets the T16_nTR register value to the counter so underflow occurs periodically Select this mode to generate periodic underflow interrupts or when us...

Page 88: ...on Clear condition Underflow T16_nINTF UFIF When the counter underflows Writing 1 T16 provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the interrupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter Contr...

Page 89: ...be selected as the clock source Note 2 When the T16_nCLK CLKSRC 1 0 bits are set to 0x3 EXCLm is selected for the channel with an event counter function or EXOSC is selected for other channels T16 Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks T16_nMOD 15 8 0x00 R 7 1 0x00 R 0 TRMD 0 H0 R W Bits 15 1 Reserved Bit 0 TRMD This bit selects the T16 operation mode 1 R W One sho...

Page 90: ... T16 Ch n operations 1 R W Enable Start supplying operating clock 0 R W Disable Stop supplying operating clock T16 Ch n Reload Data Register Register name Bit Bit name Initial Reset R W Remarks T16_nTR 15 0 TR 15 0 0xffff H0 R W Bits 15 0 TR 15 0 These bits are used to set the initial value to be preset to the counter The value set to this register will be preset to the counter when 1 is written t...

Page 91: ...e Bit Bit name Initial Reset R W Remarks T16_nINTE 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W Bits 15 1 Reserved Bit 0 UFIE This bit enables T16 Ch n underflow interrupts 1 R W Enable interrupts 0 R W Disable interrupts Note To prevent generating unnecessary interrupts clear the corresponding interrupt flag before enabling interrupts ...

Page 92: ...g error and overrun error Can generate receive buffer full 1 byte 2 bytes transmit buffer empty end of transmission parity error framing error and overrun error interrupts Input pin can be pulled up with an internal resistor The output pin is configurable as an open drain output Figure 10 1 1 shows the UART configuration Channel configuration in this IC 1 channel Ch 0 UART Ch n Interrupt control c...

Page 93: ...N bit to 1 enables the resistor to pull up the USINn pin Output Pin Open Drain Output Function 10 2 4 The USOUTn pin supports the open drain output function Default configuration is a push pull output and it is switched to an open drain output by setting the UAnMOD OUTMD bit to 1 Clock Settings 10 3 UART Operating Clock 10 3 1 When using the UART Ch n the UART Ch n operating clock CLK_UARTn must b...

Page 94: ...o calculate the setting values for obtaining the desired transfer rate CLK_UART CLK_UART bps BRT FMD 16 16 Eq 10 1 BRT 1 16 FMD bps Where CLK_UART UART operating clock frequency Hz bps Transfer rate bit s BRT UAnBR BRT 7 0 setting value 0 to 255 FMD UAnBR FMD 3 0 setting value 0 to 15 For the transfer rate range configurable in the UART refer to UART Characteristics Transfer baud rates UBRT1 and U...

Page 95: ...AnMOD CHLN bit Set 7 8 bit data length UAnMOD PREN bit Enable disable parity function UAnMOD PRMD bit Even odd parity selection UAnMOD STPB bit Set 1 2 bit stop bit length 4 Set the UAnBR BRT 7 0 and UAnBR FMD 3 0 bits Set transfer rate 5 Set the following UAnCTL register bits Set the UAnCTL SFTRST bit to 1 Execute software reset Set the UAnCTL MODEN bit to 1 Enable UART Ch n operations 6 Set the ...

Page 96: ...he UAnINTF TBSY bit is cleared to 0 and the UAnINTF TENDIF bit is set to 1 transmission completed USOUTn UAnINTF TBEIF UAnINTF TBSY UAnINTF TENDIF Software operations st D0 D1 D2 D3 D4 D5 D6 D7 p sp st D0 D1 D7 p sp st D0 D1 D7 p sp st start bit sp stop bit p parity bit Data W UAnTXD Data W UAnTXD 1 W UAnINTF TENDIF Data W UAnTXD 5 2 1 Example of Data Sending Operations Figure 10 Data transmission...

Page 97: ... UAnINTF RB1FIF bit to 1 receive buffer one byte full If the second data is received without reading the first data the UAnINTF RB2FIF bit is set to 1 receive buffer two bytes full USINn UAnINTF RB1FIF UAnINTF RB2FIF UAnINTF RBSY Software operations st D0 p sp st D0 p sp st D0 p sp st D0 p sp st start bit sp stop bit p parity bit data 1 data 2 data 3 data 4 UAnRXD data 1 R UAnRXD data 3 R UAnRXD d...

Page 98: ...t 0 UAnMOD INVIRRX bit 1 Demodulator output shift register input T2 5 4 3 IrDA Receive Signal Waveform Figure 10 Note The low pulse width T2 of the IrDA signal input must be CLK_UART 3 cycles or longer Receive Errors 10 6 Three different receive errors framing error parity error and overrun error may be detected while receiving data Since receive errors are interrupt causes they can be processed b...

Page 99: ...dition End of transmission UAnINTF TENDIF When the UAnINTF TBEIF bit 1 after the stop bit has been sent Writing 1 or software reset Framing error UAnINTF FEIF Refer to Receive Errors Writing 1 reading received data that encountered an error or software reset Parity error UAnINTF PEIF Refer to Receive Errors Writing 1 reading received data that encountered an error or software reset Overrun error U...

Page 100: ...upported in this IC cannot be selected as the clock source Note The UAnCLK register settings can be altered only when the UAnCTL MODEN bit 0 UART Ch n Mode Register Register name Bit Bit name Initial Reset R W Remarks UAnMOD 15 10 0x00 R 9 INVIRRX 0 H0 R W 8 INVIRTX 0 H0 R W 7 0 R 6 PUEN 0 H0 R W 5 OUTMD 0 H0 R W 4 IRMD 0 H0 R W 3 CHLN 0 H0 R W 2 PREN 0 H0 R W 1 PRMD 0 H0 R W 0 STPB 0 H0 R W Bits ...

Page 101: ... using the parity function 1 R W Odd parity 0 R W Even parity Bit 0 STPB This bit sets the stop bit length 1 R W 2 bits 0 R W 1 bit Note The UAnMOD register settings can be altered only when the UAnCTL MODEN bit 0 UART Ch n Baud Rate Register Register name Bit Bit name Initial Reset R W Remarks UAnBR 15 12 0x0 R 11 8 FMD 3 0 0x0 H0 R W 7 0 BRT 7 0 0x00 H0 R W Bits 15 12 Reserved Bits 11 8 FMD 3 0 ...

Page 102: ...gister Register name Bit Bit name Initial Reset R W Remarks UAnTXD 15 8 0x00 R 7 0 TXD 7 0 0x00 H0 R W Bits 15 8 Reserved Bits 7 0 TXD 7 0 Data can be written to the transmit data buffer through these bits Make sure the UAnINTF TBEIF bit is set to 1 before writing data UART Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks UAnRXD 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R Bits...

Page 103: ...n the bit and interrupt UAnINTF TENDIF bit End of transmission interrupt UAnINTF FEIF bit Framing error interrupt UAnINTF PEIF bit Parity error interrupt UAnINTF OEIF bit Overrun error interrupt UAnINTF RB2FIF bit Receive buffer two bytes full interrupt UAnINTF RB1FIF bit Receive buffer one byte full interrupt UAnINTF TBEIF bit Transmit buffer empty interrupt UART Ch n Interrupt Enable Register Re...

Page 104: ...rupt UAnINTE TENDIE bit End of transmission interrupt UAnINTE FEIE bit Framing error interrupt UAnINTE PEIE bit Parity error interrupt UAnINTE OEIE bit Overrun error interrupt UAnINTE RB2FIE bit Receive buffer two bytes full interrupt UAnINTE RB1FIE bit Receive buffer one byte full interrupt UAnINTE TBEIE bit Transmit buffer empty interrupt ...

Page 105: ...ing operated with the external input clock SPICLKn only Slave mode is capable of being operated in SLEEP mode allowing wake up by an SPI interrupt Input pins can be pulled up down with an internal resistor Figure 11 1 1 shows the SPI configuration Channel configuration in this IC Number of channels 3 channels Ch 0 Ch 1 and Ch 2 Internal clock input Ch 0 16 bit timer Ch 1 Ch 1 16 bit timer Ch 2 Ch ...

Page 106: ... SPI input output function must be assigned to the port before activating the SPI For more information refer to the I O Ports chapter External Connections 11 2 2 The SPI operates in master mode or slave mode Figures 11 2 2 1 and 11 2 2 2 show connection diagrams between the SPI in each mode and external SPI devices Px1 Px2 Px3 SDIn SDOn SPICLKn SPISS SDO SDI SPICLK SPISS SDO SDI SPICLK SPISS SDO S...

Page 107: ...SPISSn pins in slave mode have a pull up or pull down function as shown in Table 11 2 4 1 This function is enabled by setting the SPInMOD PUEN bit to 1 2 4 1 Pull Up or Pull Down of Input Pins Table 11 Pin Master mode Slave mode SDIn Pull up Pull up SPICLKn SPInMOD CPOL bit 1 Pull up SPInMOD CPOL bit 0 Pull down SPISSn Pull up Clock Settings 11 3 SPI Operating Clock 11 3 1 Operating clock in maste...

Page 108: ...g the T16_mCLK DBRUN bit The CLK_T16_m supply to the SPI Ch n is suspended when the CPU enters DEBUG mode if the T16_mCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_T16_m supply resumes Although the SPI Ch n stops operating when the CLK_T16_m supply is suspended the output pins and registers retain the status before DEBUG mode was entered If the T16_mCLK DBRUN bit 1 the CLK_T16_m sup...

Page 109: ...bit Select master mode operating clock SPInMOD LSBFST bit Select MSB first LSB first SPInMOD CPHA bit Select clock phase SPInMOD CPOL bit Select clock polarity SPInMOD MST bit Select master slave mode 3 Assign the SPI Ch n input output function to the ports Refer to the I O Ports chapter 4 Set the following SPInCTL register bits Set the SPInCTL SFTRST bit to 1 Execute software reset Set the SPInCT...

Page 110: ...he next transmit data can be written to the SPInTXD register after making sure the SPInINTF TBEIF bit is set to 1 If transmit data has not been written to the SPInTXD register after the eighth clock is output from the SPICLKn pin the clock output halts and the SPInINTF TENDIF bit is set to 1 At the same time the SPI issues an end of transmission interrupt request if the SPInINTE TENDIE bit 1 SPICL...

Page 111: ...ving operations simultaneously with data sending operations when transmit data may be dummy data if data transmission is not required is written to the SPInTXD register The SPICLKn pin outputs eight clocks The transmit data bits are output in sequence from the SDOn pin in sync with this clock and the receive data bits input from the SDIn pin are shifted into the shift register When the eighth cloc...

Page 112: ... Reception Flowcharts in Master Mode Figure 11 Terminating Data Transfer in Master Mode 11 5 4 A procedure to terminate data transfer in master mode is shown below 1 Wait for an end of transmission interrupt SPInINTF TENDIF bit 1 2 Set the SPInCTL MODEN bit to 0 to disable the SPI Ch n operations 3 Stop the 16 bit timer to disable the clock supply to the SPI Ch n Data Transfer in Slave Mode 11 5 5...

Page 113: ...g data reception only Data transmission reception can be performed even in SLEEP mode it makes it possible to wake the CPU up using an SPI interrupt Other operations are the same as master mode Notes If 8 bit data is received when the SPInINTF RBFIF bit is set to 1 the SPInRXD register is over written with the newly received 8 bit data and the previously received data is lost There is no flag prov...

Page 114: ...a buffer Reading the SPIn RXD register Transmit buffer empty SPInINTF TBEIF When transmit data written to the transmit data buf fer is transferred to the shift register Writing to the SPInTXD register The SPI provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the inter rupt controller only when the interrupt flag of which interrupt has been enabled ...

Page 115: ...ctive in slave mode 1 R W SPICLKn frequency CLK_SPIn frequency 16 bit timer operating clock frequency 0 R W SPICLKn frequency 16 bit timer output frequency 2 For more information refer to SPI Operating Clock Bit 3 LSBFST This bit configures the data format input output permutation 1 R W LSB first 0 R W MSB first Bit 2 CPHA Bit 1 CPOL These bits set the SPI clock phase and polarity For more informa...

Page 116: ...D 7 0 0x00 H0 R W Bits 15 8 Reserved Bits 7 0 TXD 7 0 Data can be written to the transmit data buffer through these bits In master mode writing to these bits starts data transfer Transmit data can be written when the SPInINTF TBEIF bit 1 regardless of whether data is being output from the SDOn pin or not Note Be sure to avoid writing to the SPInTXD register when the SPInINTF TBEIF bit 0 Otherwise ...

Page 117: ...the bit and interrupt SPInINTF TENDIF bit End of transmission interrupt SPInINTF RBFIF bit Receive buffer full interrupt SPInINTF TBEIF bit Transmit buffer empty interrupt SPI Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks SPInINTE 15 8 0x00 R 7 3 0x00 R 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W Bits 15 3 Reserved Bit 2 TENDIE Bit 1 RBFIE Bit 0 TBEIE ...

Page 118: ...an interrupt when an address match is detected Master mode supports automatic bus clear sending function Can generate receive buffer full transmit buffer empty and other interrupts Figure 12 1 1 shows the I2C configuration Channel configuration in this IC 1 channel Ch 0 I2C Ch n Interrupt control circuit BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE CLKSRC 1 0 CLKDIV 1 0 Transmit receive ...

Page 119: ...ines must be pulled up with an external resistor When the I2C is set into master mode one or more slave devices that have a unique address may be connected to the I2C bus When the I2C is set into slave mode one or more master and slave devices that have a unique address may be connected to the I2C bus SCLn VDD SDAn S1C17 Serial data SDA Serial clock SCL I2C bus External I2C device External I2C dev...

Page 120: ...aster mode the CLK_I2Cn supply during DEBUG mode should be controlled using the I2CnCLK DBRUN bit The CLK_I2Cn supply to the I2C Ch n is suspended when the CPU enters DEBUG mode if the I2CnCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_I2Cn supply resumes Although the I2C Ch n stops oper ating when the CLK_I2Cn supply is suspended the output pin and registers retain the status before...

Page 121: ...er mode 1 Configure the operating clock and the baud rate generator using the I2CnCLK and I2CnBR registers 2 Assign the I2C Ch n input output function to the ports Refer to the I O Ports chapter 3 Set the following bits when using the interrupt Write 1 to the interrupt flags in the I2CnINTF register Clear interrupt flags Set the interrupt enable bits in the I2CnINTE register to 1 Enable interrupts...

Page 122: ...dition when the I2CnCTL TXSTART bit is set to 1 When the generating operation has completed the I2C Ch n clears the I2CnCTL TXSTART bit to 0 and sets both the I2CnINTF STARTIF and I2CnINTF TBEIF bits to 1 Sending slave address and data If the I2CnINTF TBEIF bit 1 a slave address or data can be written to the I2CnTXD register The I2C Ch n pulls down SCL to low and enters standby state until data is...

Page 123: ...y the external slave Standby state SCL low TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A S TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 0 STARTIF 1 TBEIF 1 TXSTART 1 TXSTOP 1 TXSTOP 0 STOPIF 1 P A TXSTART 1 Sr A TBEIF 1 TBEIF 1 NACKIF 1 NACKIF 1 NACKIF 1 4 2 1 Example of Data Sending Operations in Master Mode Figure 12 Data transmission End Write slave address and WRITE 0 to the I2CnTXD register ...

Page 124: ...st data is received and then go to Step 6 ii When the last data is received read the received data from the I2CnRXD register and set the I2CnCTL TXSTOP to 1 to generate a STOP condition Then go to Step 8 6 Read the received data from the I2CnRXD register 7 Repeat Steps 4 to 6 until the end of data reception 8 Wait for a STOP condition interrupt I2CnINTF STOPIF bit 1 Clear the I2CnINTF STOPIF bit b...

Page 125: ...ndition P STOP condition A ACK A NACK Saddr R Slave address R 1 Data n 8 bit data Hardware bit operations Operations by the external slave Standby state SCL low RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 RBFIF 1 TXNACK 0 4 3 1 Example of Data Receiving Operations in Master Mode Figure 12 Data reception End Write slave address and READ 1 to the I2CnTXD register Write 1 to the I2CnCTL TXSTOP bit Write 1 to t...

Page 126: ...ition by setting the I2CnCTL TXSTART bit to 1 2 Wait for a transmit buffer empty interrupt I2CnINTF TBEIF bit 1 or a START condition interrupt I2C nINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 3 Write the first address to the I2CnTXD TXD 7 1 bits and 0 that represents WRITE as the data transfer di rection to the I2CnTXD TXD0 bit 4 Wait for a trans...

Page 127: ...ending procedure in slave mode and the I2C Ch n operations are shown below Figures 12 4 5 1 and 12 4 5 2 show an operation example and a flowchart respectively Data sending procedure 1 Wait for a START condition interrupt I2CnINTF STARTIF bit 1 Clear the I2CnINTF STARTIF bit by writing 1 after the interrupt has occurred 2 Check to see if the I2CnINTF TR bit 1 transmission mode Start a data receivi...

Page 128: ...ng data transmission If the I2CnINTF TBEIF bit is still set to 1 when the data transmission from the shift register has completed the I2C Ch n pulls down SCL to low sets the I2C bus into clock stretching state until transmit data is written to the I2CnTXD register If the next transmit data already exists in the I2CnTXD register or data has been written after the above the I2C Ch n sends the subseq...

Page 129: ... 0 and the I2CnINTF TBEIF bit is not set If the I2CnMOD GCEN bit is set to 1 general call address response enabled the I2C Ch n starts data re ceiving operations when the general call address is received Slave mode can be operated even in SLEEP mode it makes it possible to wake the CPU up using an inter rupt when an address match is detected Receiving the first data byte After the valid slave addr...

Page 130: ... N TXNACK 1 RXD 7 0 Data N 1 RXD 7 0 Data N RBFIF 1 BYTEENDIF 1 RBFIF 1 BYTEENDIF 1 I2C bus Clock stretching by I2C Software bit operations Operations by the external master S START condition Sr Repeated START condition P STOP condition A ACK A NACK Saddr W Slave address W 0 Data n 8 bit data Hardware bit operations Operations by I2C slave mode BSY 0 TXNACK 0 STOPIF 1 TR 0 STARTIF 1 BSY 1 TXNACK 0...

Page 131: ...mode A 1stAddr W A 2ndAddr A 1stAddr W A 2ndAddr At start of data transmission At start of data reception S STARTIF 1 STARTIF 1 A Data 1 A Data 2 I2C bus Clock stretching by I2C I2C bus Clock stretching by I2C Software bit operations Operations by I2C master mode S START condition Sr Repeated START condition P STOP condition A ACK A NACK 1stAddr W 1st address W 0 1stAddr R 1st address R 1 2ndAddr ...

Page 132: ...ormed The table below lists the hardware error detection conditions and the notification method 4 9 1 Table 12 Hardware Error Detection Function No Error detecting period timing I2C bus line monitored and error condition Notification method 1 While the I2C Ch n controls SDA to high for sending address data or a NACK SDA low I2CnINTF ERRIF 1 2 Master mode only When 1 is written to the I2CnCTL TX ST...

Page 133: ...s issued Slave mode When an address match is detected including general call Writing 1 software reset Error detection I2CnINTF ERRIF Refer to Error Detection Writing 1 software reset Receive buffer full I2CnINTF RBFIF When received data is loaded to the receive data buffer Reading received data to empty the receive data buffer software reset Transmit buffer empty I2CnINTF TBEIF Master mode When a ...

Page 134: ...0 0x0 H0 R W Bits 15 9 Reserved Bit 8 DBRUN This bit sets whether the I2C operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the I2C operating clock Bits 3 2 Reserved Bits 1 0 CLKSRC 1 0 These bits select the clock source of the I2C 6 1 Clock Source a...

Page 135: ...ster name Bit Bit name Initial Reset R W Remarks I2CnBR 15 8 0x00 R 7 0 R 6 0 BRT 6 0 0x7f H0 R W Bits 15 7 Reserved Bits 6 0 BRT 6 0 These bits set the I2C Ch n transfer rate for master mode For more information refer to Baud Rate Generator Notes The I2CnBR register settings can be altered only when the I2CnCTL MODEN bit 0 Be sure to avoid setting the I2CnBR register to 0 I2C Ch n Own Address Reg...

Page 136: ...TOP condition 0 R STOP condition has been generated This bit is automatically cleared when the bus free time tBUF defined in the I2C Specifications has elapsed after the STOP condition has been generated Bit 2 TXSTART This bit issues a START condition in master mode This bit is ineffective in slave mode 1 W Issue a START condition 0 W Ineffective 1 R On standby or during generating a START conditi...

Page 137: ...er when the I2CnINTF TBEIF bit 0 otherwise transmit data cannot be guaranteed I2C Ch n Receive Data Register Register name Bit Bit name Initial Reset R W Remarks I2CnRXD 15 8 0x00 R 7 0 RXD 7 0 0x00 H0 R Bits 15 8 Reserved Bits 7 0 RXD 7 0 The receive data buffer can be read through these bits I2C Ch n Status and Interrupt Flag Register Register name Bit Bit name Initial Reset R W Remarks I2CnINTF...

Page 138: ...t occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt I2CnINTF BYTEENDIF bit End of transfer interrupt I2CnINTF GCIF bit General call address reception interrupt I2CnINTF NACKIF bit NACK reception interrupt I2CnINTF STOPIF bit STOP condition interrupt I2CnINTF STARTIF bit START condition interrupt I2CnINTF ...

Page 139: ...s The following shows the correspondence between the bit and interrupt I2CnINTE BYTEENDIE bit End of transfer interrupt I2CnINTE GCIE bit General call address reception interrupt I2CnINTE NACKIE bit NACK reception interrupt I2CnINTE STOPIE bit STOP condition interrupt I2CnINTE STARTIE bit START condition interrupt I2CnINTE ERRIE bit Error detection interrupt I2CnINTE RBFIE bit Receive buffer full ...

Page 140: ...es F256 256 Hz regulated clock which is generated by the clock generator from OSC1 as the clock source as its operating clock CT is operable when OSC1 is enabled When using CT during SLEEP mode the clock must be configured so that it will keep supplying by writing 0 to the CLGOSC OSC1SLPC bit Operations 13 3 Follow the sequences shown below to start counting of CT and to read the counter Count sta...

Page 141: ... Table 13 Interrupt Interrupt flag Set condition Clear condition 32 Hz CTINTF CT32HZIF Signal falling edge See Figure 13 4 1 Writing 1 8 Hz CTINTF CT8HZIF Writing 1 2 Hz CTINTF CT2HZIF Writing 1 1 Hz CTINTF CT1HZIF Writing 1 256 Hz 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt 1 Hz interrupt Count clock CTDAT CTCNT0 CTDAT CTCNT1 CTDAT CTCNT2 CTDAT CTCNT...

Page 142: ...p control When CT stops counting by writing 0 to this bit the counter retains the value when it stopped Writ ing 1 to this bit again resumes counting from the value retained CT Counter Data Register Register name Bit Bit name Initial Reset R W Remarks CTDAT 15 8 0x00 R 7 0 CTCNT 7 0 0x00 H0 S0 R Bits 15 8 Reserved Bits 7 0 CTCNT 7 0 The counter data can be read through these bits The bits correspo...

Page 143: ...ws the correspondence between the bit and interrupt CTINTF CT32HZIF bit 32 Hz interrupt CTINTF CT8HZIF bit 8 Hz interrupt CTINTF CT2HZIF bit 2 Hz interrupt CTINTF CT1HZIF bit 1 Hz interrupt CT Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks CTINTE 15 8 0x00 R 7 4 0x0 R 3 CT32HZIE 0 H0 R W 2 CT8HZIE 0 H0 R W 1 CT2HZIE 0 H0 R W 0 CT1HZIE 0 H0 R W Bits 15 4 Reserved Bit...

Page 144: ...DMD AMPM HDIF 1HIF 10MIF 1MIF 10SIF 1HZIF 4HZIF 8HZIF 32HZIF Internal data bus F256 Clock generator and Theoretical regulation 1 1 RTC Configuration Figure 14 Clock Settings 14 2 RTC uses F256 256 Hz regulated clock which is generated by the clock generator from OSC1 as the clock source as its operating clock RTC is operable when OSC1 is enabled When using RTC during SLEEP mode the clock must be c...

Page 145: ...R 3 0 BCD mode 0 9 1 hour digit RTCHUR 5 4 0 2 10 hour digit RTCHUR 5 0 12H mode 1 12 RTCHUR 3 0 0 9 1 hour digit RTCHUR 5 4 0 1 10 hour digit 3 3 Hour Counter Figure 14 3 1 Hour Counter Values Table 14 Time 24H mode 12H mode RTCHUR 5 0 binary RTCHUR 5 0 BCD RTCHUR 5 0 binary RTCHUR 5 0 BCD AMPM 0 o clock 12am 0x0 0x00 0xc 0x12 0 1 o clock 1am 0x1 0x01 0x1 0x01 0 2 o clock 2am 0x2 0x02 0x2 0x02 0 ...

Page 146: ...unter setting END RTCCTL RTCST 0 4 1 1 Counter Setting Procedure Figure 14 Notes An initial reset does not initialize the second minute hour counter values Be sure to initialize the counters via software Do not set the counters while the RTC is running RTCCTL RTCST bit 1 as proper settings to the counters cannot be guaranteed Counter values to be set must be within the effective range according to...

Page 147: ... 14 5 1 5 1 RTC Interrupt Function Table 14 Interrupt Interrupt flag Set condition Clear condition One day RTCINTF 1DIF Hour counter 23 0 24H mode Hour counter PM11 AM12 12H mode Writing 1 Half day RTCINTF HDIF Hour counter 11 12 23 0 24H mode Hour counter AM11 PM12 PM11 AM12 12H mode Writing 1 1 hour RTCINTF 1HIF Minute counter 59 0 Writing 1 10 minutes RTCINTF 10MIF Minute counter 9 10 19 20 29 ...

Page 148: ...ed to 0 before writing data Bits 7 6 Reserved Bit 5 BCDMD This bit sets the second minute and hour counters into binary or BCD mode 1 R W BCD mode 0 R W Binary mode See RTC Counters for the configuration of the counter in each mode Bit 4 RTC24H This bit sets the hour counter to 24H mode or 12H mode 1 R W 12H mode 0 R W 24H mode This selection changes the count range of the hour counter Note howeve...

Page 149: ...R W Disable interrupts The following shows the correspondence between the bit and interrupt RTCINTE 1DIE bit One day interrupt RTCINTE HDIE bit Half day interrupt RTCINTE 1HIE bit 1 hour interrupt RTCINTE 10MIE bit 10 minutes interrupt RTCINTE 1MIE bit 1 minute interrupt RTCINTE 10SIE bit 10 seconds interrupt RTCINTE 1HZIE bit 1 Hz interrupt RTCINTE 4HZIE bit 4 Hz interrupt RTCINTE 8HZIE bit 8 Hz ...

Page 150: ...F 4HZIF bit 4 Hz interrupt RTCINTF 8HZIF bit 8 Hz interrupt RTCINTF 32HZIF bit 32 Hz interrupt RTC Minute Second Register Register name Bit Bit name Initial Reset R W Remarks RTCMIN 15 0 R 14 8 RTCMIN 6 0 x R W 7 0 R 6 0 RTCSEC 6 0 x R W Note Be sure to avoid writing to this register while the RTCCTL RTCST bit 1 Bit 15 Reserved Bits 14 8 RTCMIN 6 0 These bits are used to read and write data from t...

Page 151: ... 1 R W P M 0 R W A M In 24H mode RTCCTL RTC24H bit 0 this bit is fixed at 0 In this case do not write 1 to the RTCHUR AMPM bit Note The RTCHUR AMPM bit will be fixed at 0 immediately after the RTCCTL RTC24H bit is changed from 12 hour mode to 24 hour mode Bit 6 Reserved Bits 5 0 RTCHUR 5 0 These bits are used to read and write data from to the hour counter For the configuration of the hour counter...

Page 152: ... 256 Hz F256 256 Hz F1 1 Hz RTC reset To peripheral circuits OSC1A oscillator 32 768 kHz Clock generator OSC1A divider REGMON 1 1 TR Configuration Figure 15 Output Pin 15 2 Table 15 2 1 shows the TR output pin 2 1 TR Output Pin Table 15 Pin name I O Initial status Function REGMON O O L Theoretical regulation clock monitor output Indicates the status when the pin is configured for TR If the port is...

Page 153: ...2 5 801 0x36 9 2 373 0x16 23 6 064 0x37 8 2 109 0x17 24 6 328 0x38 7 1 846 0x18 25 6 592 0x39 6 1 582 0x19 26 6 855 0x3a 5 1 318 0x1a 27 7 119 0x3b 4 1 055 0x1b 28 7 383 0x3c 3 0 791 0x1c 29 7 646 0x3d 2 0 527 0x1d 30 7 910 0x3e 1 0 264 0x1e 31 8 174 0x3f 0 0 0x1f 32 8 438 Rates when theoretical regulation is executed in 10 second cycles n 32 768 6 times minute 60 minutes 24 hours The correction v...

Page 154: ...l Register 15 4 Theoretical Regulation Control Register Register name Bit Bit name Initial Reset R W Remarks TRCTL 15 10 0x00 R 9 REGFREQ 0 H0 R W 8 REGMONEN 0 H0 R W 7 REGTRIG 0 H0 W Always read as 0 6 0 R 5 0 TRIM 5 0 0x00 H0 R W Bits 15 10 Reserved Bit 9 REGFREQ This bit selects the frequency of the regulated clock to be output from the REGMON pin for monitor ing 1 R W 1 Hz F1 0 R W 256 Hz F256...

Page 155: ...ICAL REGULATION TR 15 4 Seiko Epson Corporation S1C17F13 Technical Manual Rev 1 0 Bit 6 Reserved Bits 5 0 TRIM 5 0 These bits specify the correction value 31 32 768 to 32 32 768 seconds for theoretical regulation ...

Page 156: ...wo specified values to generate interrupt signals and a PWM waveform Can be used as an interval timer PWM waveform generator and external event counter The capture unit captures counter values using external trigger signals and generates interrupts Can be used to measure external event periods Multi comparator capture mode One counter can be used with two or more comparator capture blocks con nect...

Page 157: ... lists the T16A3 pins 2 1 List of T16A3 Pins Table 16 Pin name I O Initial status Function EXCLm I I Hi Z External clock input TOUTAn CAPAn TOUTBn CAPBn O or I O Low TOUTA B signal output in comparator mode or capture A B trigger signal input in capture mode Indicates the status when the pin is configured for T16A3 If the port is shared with the T16A3 pin and other functions the T16A3 input output...

Page 158: ...ed using the T16AnCLK CLKSRC 1 0 bits The counter counts up at the rising edge of the EXCLm input signal EXCLm pin input Counter x x 1 x 2 x 3 3 4 1 Count Up Timing Figure 16 Operations 16 4 Initialization 16 4 1 T16A3 Ch n should be initialized and started counting with the procedure shown below Perform initial settings for comparator mode when using T16A3 as an interval timer PWM waveform genera...

Page 159: ...counter Set the T16AnCTL MODEN bit to 1 Enable count operations Set the T16AnCTL PRUN bit to 1 Start counting Counter Block Operations 16 4 2 The counter in each counter block channel is a 16 bit up counter that counts the selected operating clock count clock Counter reset Setting the T16AnCTL PRESET bit to 1 clears the counter to 0 In comparator mode the counter is also cleared to 0 by the compar...

Page 160: ...e values are matched The T16AnCCA and or T16AnCCB registers function as the compare A and or compare B registers that are used for setting compare values in this mode Furthermore the TOUTAn CAPAn pin and the TOUTBn CAPBn pin are configured to the TOUTAn pin and the TOUTBn pin respectively When the counter reaches the value set in the T16AnCCA register during counting the comparator asserts the com...

Page 161: ...e compare A and B buffer values instead of the T16AnCCA and T16AnCCB register values The T16AnCCA and T16AnCCB register values written via software are loaded to the compare A and compare B buffers when the compare B signal is generated when the T16AnCTL CBUFEN bit is set to 0 the T16AnCCA and T16AnCCB register values are loaded to the compare buffers simultaneously with writing 0xffff 0x0000 When...

Page 162: ...es The correct captured data may not be obtained if the captured data is read at the same time the next value is being captured Read the T16AnCCA or T16AnCCB register twice to check if the read data is correct as necessary To capture counter data properly both the high and low period of the CAPAn CAPBn trigger signal must be longer than the source clock cycle time Counter CAPAn input 0xffff 0x0000...

Page 163: ... channels Figure 16 Counter block Ch 1 Comparator capture block Ch 1 Counter block Ch 0 Comparator capture block Ch 0 Counter block Ch 2 Comparator capture block Ch 2 Counter block Ch 3 Comparator capture block Ch 3 T16A3 CLK_T16A1 CLK_T16A0 CLK_T16A2 CLK_T16A3 Counter block Ch 1 Comparator capture block Ch 1 Counter block Ch 0 Comparator capture block Ch 0 T16A3 Counter block Ch 2 Comparator capt...

Page 164: ...ly Although the output circuit and register names use letters A and B to distinguish two systems it does not mean that they correspond to compare A and B TOUT generation mode The T16AnCCCTL TOUTAMD 1 0 bits for system A or the T16AnCCCTL TOUTBMD 1 0 bits for system B are used to set how the TOUT signal waveform is changed by the compare A and compare B signals These bits are also used to turn the ...

Page 165: ...16AnCCB register setting value must be less than T16AnCCA set ting value 2 0x8000 The compare B value T16AnCCB register value will be compared with the T16AnTC counter value even if T16A3 Ch n is set to half clock mode Count clock T16AnTC T16ATC 15 0 TOUTAn TOUTBn T16AnCCA CCA 15 0 When T16AnCCCTL TOUTAMD 1 0 TOUTBMD 1 0 0x1 and T16AnCCCTL TOUTAINV TOUTBINV 0 n 0 0 1 2 n 1 n 0 1 1 2 n 2 n 1 n T16A...

Page 166: ...fer value in comparator mode Writing 1 T16A3 provides interrupt enable bits corresponding to each interrupt flag An interrupt request is sent to the inter rupt controller only when the interrupt flag of which interrupt has been enabled by the interrupt enable bit is set For more information on interrupt control refer to the Interrupt Controller chapter Control Registers 16 6 T16A3 Ch n Clock Contr...

Page 167: ...unction or EXOSC is selected for other channels T16A3 Counter Ch n Control Register Register name Bit Bit name Initial Reset R W Remarks T16AnCTL 15 9 0x00 R 8 PRUN 0 H0 R W 7 X R Read value is undefined 6 HCM 0 H0 R W 5 4 CCABCNT 1 0 0x0 H0 R W 3 CBUFEN 0 H0 R W 2 TRMD 0 H0 R W 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W Bits 15 9 Reserved Bit 8 PRUN This bit starts stops counting 1 W Start counting 0 W S...

Page 168: ...ormation refer to Comparator Capture Block Operations Compare buffers Note Make sure the counter is halted T16AnCTL PRUN bit 0 before setting the T16AnCTL CBUFEN bit Bit 2 TRMD This bit selects the count mode 1 R W One shot mode 0 R W Repeat mode For detailed information refer to Counter Block Operations Count mode repeat mode and one shot mode Bit 1 PRESET This bit resets the counter 1 W Reset 0 ...

Page 169: ...UTBMD 1 0 These bits configure how the TOUTB signal waveform TOUTBn output is changed by the compare A and compare B signals These bits are also used to turn the TOUTB output on and off 6 4 TOUTB Signal Generation Mode Table 16 T16AnCCCTL TOUTBMD 1 0 bits When compare A occurs When compare B occurs 0x3 No change Toggle 0x2 Toggle No change 0x1 Rise Fall 0x0 Disable output The T16AnCCCTL TOUTBMD 1 ...

Page 170: ...OUTAINV bit is a control bit for comparator mode and are ineffective in capture mode Bit 0 CCAMD This bit selects the T16AnCCA register operating mode 1 R W Capture mode T16AnCCA register capture A register 0 R W Comparator mode T16AnCCA register compare A register T16A3 Comparator Capture Ch n A Data Register Register name Bit Bit name Initial Reset R W Remarks T16AnCCA 15 0 CCA 15 0 0x0000 H0 R ...

Page 171: ...s 15 6 Reserved Bit 5 CAPBOWIF Bit 4 CAPAOWIF Bit 3 CAPBIF Bit 2 CAPAIF Bit 1 CMPBIF Bit 0 CMPAIF These bits indicate the T16A3 Ch n interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of interrupt occurred 1 W Clear flag 0 W Ineffective The following shows the correspondence between the bit and interrupt T16AnINTF CAPBOWIF bit Capture B overwrite interrupt T16AnINTF CAP...

Page 172: ...upts The following shows the correspondence between the bit and interrupt T16AnINTE CAPBOWIE bit Capture B overwrite interrupt T16AnINTE CAPAOWIE bit Capture A overwrite interrupt T16AnINTE CAPBIE bit Capture B interrupt T16AnINTE CAPAIE bit Capture A interrupt T16AnINTE CMPBIE bit Compare B interrupt T16AnINTE CMPAIE bit Compare A interrupt Note To prevent generating unnecessary interrupts clear ...

Page 173: ...WDATA 7 0 Read data PRDATA 7 0 Clock generator DBRUN MODEN CLK_PIO PUL GPIOMD SFTRST WBUSY RBUSY RACC PIOCE PIORD PIOWR PIOA 7 0 PIOD 7 0 Internal data bus I O cell 1 1 PIO Configuration Figure 17 Input Output Pins and External Connections 17 2 List of Input Output Pins 17 2 1 Table 17 2 1 1 lists the PIO pins 2 1 1 List of PIO Pins Table 17 Pin name I O Initial status Function PIOA 7 0 O O Low PI...

Page 174: ...CLKSRC 1 0 bits Clock source selection PIOCLK CLKDIV 1 0 bits Clock division ratio selection Clock frequency setting Clock Supply in SLEEP Mode 17 3 2 When using PIO during SLEEP mode the PIO operating clock CLK_PIO must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the CLK_PIO clock source Clock Supply in DEBUG Mode 17 3 3 The CLK_PIO supply during DEBUG...

Page 175: ...ed within one CLK_PIO clock cycle This starts a data write cycle After one clock cycle from the trigger sampling PIO asserts the PIOCE signal and outputs the address and data from the PIOA 7 0 pins and the PIOD 7 0 pins respectively The PIOSTAT WBUSY bit is also set to 1 write cycle busy status PIO asserts the PIOWR signal while the access cycle one CLK_PIO clock cycle after the setup cycle one CL...

Page 176: ...atus Trigger signal CLK_PIO PIOCE PIORD PIOA 7 0 PIOD 7 0 PIORDDAT PRDATA 7 0 PIOSTAT RBUSY State Sampling clear PIOCTL RACC 1 Idle Setup Access Hold Idle PIOWRDAT PADDR 7 0 4 2 2 Data Read Timing Figure 17 Operations in GPIO Mode 17 4 3 In GPIO mode PIOMOD GPIOMD bit 1 the address bus pins and data bus pins are configured as eight bits of general purpose output ports and eight bits of general pur...

Page 177: ...served Bits 1 0 CLKSRC 1 0 These bits select the clock source of PIO 5 1 Clock Source and Division Ratio Settings Table 17 PIOCLK CLKDIV 1 0 bits PIOCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 OSC3B OSC1 OSC3A EXOSC 0x3 1 8 1 8 1 8 1 1 0x2 1 4 1 4 1 4 0x1 1 2 1 2 1 2 0x0 1 1 1 1 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source Note T...

Page 178: ...topped Note If the PIOCTL MODEN bit is altered from 1 to 0 while a bus cycle is being executed the input output data cannot be guaranteed When setting the PIOCTL MODEN bit to 1 again after that be sure to write 1 to the PIOCTL SFTRST bit as well PIO Address Write Data Register Register name Bit Bit name Initial Reset R W Remarks PIOWRDAT 15 8 PADDR 7 0 0x00 H0 R W 7 0 PWDATA 7 0 0x00 H0 R W Bits 1...

Page 179: ...l the read cycle has finished PIOSTAT RBUSY bit changes 1 to 0 PIO Status Register Register name Bit Bit name Initial Reset R W Remarks PIOSTAT 15 8 0x00 R 7 2 0x00 R 1 WBUSY 0 H0 S0 R 0 RBUSY 0 H0 S0 R Bits 15 2 Reserved Bit 1 WBUSY This bit indicates the write cycle operating status 1 R Write cycle is being executed 0 R Idle Bit 0 RBUSY This bit indicates the read cycle operating status 1 R Read...

Page 180: ...nd all the EPD Tcon functions can be controlled using the API For the data format in the display RAM various settings and operations refer to the descriptions of the EPD Tcon API library EPD Timing Controller S1C17F13 Manual separately attached sheet Note EPD Tcon occupies SPI Ch 1 or the parallel interface while it is running This peripheral circuit cannot be accessed from the S1C17 Interrupt 18 ...

Page 181: ...ame Bit Bit name Initial Reset R W Remarks EPDINTF 15 9 0x00 R 8 BUSY 1 H0 R 7 1 0x00 R 0 ENDIF 0 H0 R W Cleared by writing 1 Bits 15 9 Reserved Bit 8 BUSY This bit indicates the EPD Tcon operating status 1 R Operating During display data transfer 0 R Idle Bits 7 1 Reserved Bit 0 ENDIF This bit indicates the EPD Tcon interrupt cause occurrence status 1 R Cause of interrupt occurred 0 R No cause of...

Page 182: ...er hygrometer can be easily implemented by connecting a thermistor or a humidity sensor and a few passive elements resistor and capacitor Allows measurement counting by inputting external clocks Provides an output and continuous oscillation function for monitoring the oscillation frequency Can generate reference oscillation completion sensor A and B oscillation completion measurement counter overf...

Page 183: ...efore activating the RFC For more information refer to the I O Ports chapter Note The RFINn pin goes to VSS level when the port is switched Be aware that large current may flow if the pin is biased by an external circuit External Connections 19 2 2 The figures below show connection examples between the RFC and external sensors For the oscillation mode and external clock input mode refer to Operati...

Page 184: ... Supply in SLEEP Mode 19 3 2 When using RFC during SLEEP mode the RFC operating clock TCCLK must be configured so that it will keep supplying by writing 0 to the CLGOSC xxxxSLPC bit for the TCCLK clock source Clock Supply in DEBUG Mode 19 3 3 The TCCLK supply during DEBUG mode should be controlled using the RFCnCLK DBRUN bit The TCCLK supply to the RFC is suspended when the CPU enters DEBUG mode i...

Page 185: ...nput threshold voltage VT and Low level Schmitt input thresh old voltage VT in the Electrical Characteristics chapter This function is enabled by setting the RFCnCTL EVTEN bit to 1 The measurement procedure is the same as when the internal oscillation circuit is used RFC Counters 19 4 3 The RFC incorporates two counters shown below Measurement counter MC The measurement counter is a 24 bit presett...

Page 186: ...IF bit and then go to Step 6 ii If the RFCnINTF OVTCIF bit 1 time base counter overflow error clear the RFCnINTF OVTCIF bit and terminate measurement as an error or retry after altering the measurement counter initial value 6 Clear the RFCnINTF ESENAIF RFCnINTF ESENBIF and RFCnINTF OVMCIF bits by writing 1 7 Set the RFCnTRG SSENA bit sensor A or the RFCnTRG SSENB bit sensor B corresponding to the ...

Page 187: ...oint Max count value 0xffffff Min count value 0x000000 Max count value 0xffffff Min count value 0x000000 Overflow normal termination EREFIF 1 SREF 0 Overflow error termination OVMCIF 1 SSENx 0 Count value m1 Count value m2 Varies depending on the environment Calculate the sensor detecting value from the measurement counter value m1 and m2 Overflow error termination OVTCIF 1 SREF 0 Underflow normal...

Page 188: ...FCnCTL CONEN Writing 1 Writing 0 4 5 1 CR Oscillation Clock RFCLK Waveform Figure 19 Interrupts 19 5 The RFC has a function to generate the interrupts shown in Table 19 5 1 5 1 RFC Interrupt Function Table 19 Interrupt Interrupt flag Set condition Clear condition Reference oscillation completion RFCnINTF EREFIF When reference oscillation has been completed normally due to a measurement counter ove...

Page 189: ...k source of the RFC 6 1 Clock Source and Division Ratio Settings Table 19 RFCnCLK CLKDIV 1 0 bits RFCnCLK CLKSRC 1 0 bits 0x0 0x1 0x2 0x3 OSC3B OSC1 OSC3A EXOSC 0x3 1 8 1 1 0x2 1 4 0x1 1 2 0x0 1 1 Note The oscillation circuits external input that are not supported in this IC cannot be selected as the clock source Note The RFCnCLK register settings can be altered only when the RFCnCTL MODEN bit 0 R...

Page 190: ...sor measurements 0x0 DC oscillation mode for resistive sensor measurements Bits 3 1 Reserved Bit 0 MODEN This bit enables the RFC operations 1 R W Enable RFC operations The operating clock is supplied 0 R W Disable RFC operations The operating clock is stopped Note If the RFCnCTL MODEN bit is altered from 1 to 0 during R F conversion the counter value being converted cannot be guaranteed R F conve...

Page 191: ...Register name Bit Bit name Initial Reset R W Remarks RFCnMCL RFCnMCH 31 24 0x00 R 23 0 MC 23 0 0x000000 H0 R W Bits 31 24 Reserved Bits 23 0 MC 23 0 Measurement counter data can be read and written through these bits Note The measurement counter must be set from the low order value RFCnMCL MC 15 0 bits first when data is set using a 16 bit access instruction The counter may not be set to the corre...

Page 192: ...pt RFCnINTF ESENBIF bit Sensor B oscillation completion interrupt RFCnINTF ESENAIF bit Sensor A oscillation completion interrupt RFCnINTF EREFIF bit Reference oscillation completion interrupt RFC Ch n Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks RFCnINTE 15 8 0x00 R 7 5 0x0 R 4 OVTCIE 0 H0 R W 3 OVMCIE 0 H0 R W 2 ESENBIE 0 H0 R W 1 ESENAIE 0 H0 R W 0 EREFIE 0 H0 R...

Page 193: ... digital value 8 bits conversion circuit Conversion time comparison time adjustment function TEM compares the sensor detection voltage with the reference voltage Can generate conversion completion interrupts Figure 20 1 1 shows TEM configuration Comparison voltage setting circuit Temperature sensor Comparator Comparison time setting circuit TEM Interrupt control circuit MODEN CVTM 7 0 TEMTRG TEMIE...

Page 194: ...the TEMCLK DBRUN bit The CLK_TEM supply to TEM is suspended when the CPU enters DEBUG mode if the TEMCLK DBRUN bit 0 After the CPU returns to normal mode the CLK_TEM supply resumes Although TEM stops operating when the CLK_TEM supply is suspended the registers retain the status before DEBUG mode was entered If the TEMCLK DBRUN bit 1 the CLK_TEM supply is not suspended and TEM will keep operating i...

Page 195: ...e results to the TEMRSLT TEMP 7 0 bits The following shows the conversion time Conversion time Comparison time Eq 20 1 8 Eq 20 2 Example Conversion time 1 200 µs when Comparison time 150 µs The TEMINTF TEMST bit is set to 1 during converting operation and reverts to 0 after the conversion has fin ished Note however that a maximum one CLK_TEM cycle of delay occurs until the TEMINTF TEMST bit is set...

Page 196: ...x6c 69 2 0xa0 20 2 0x6b 70 1 0x9f 21 2 0x6b 0x0 Invalid 0x9e 22 1 0x9d 23 1 0x9c 24 0 0x9b 25 0 0x9a 26 0 0x99 26 9 0x98 27 9 0x97 28 8 0x96 29 8 0xca 20 3 0x95 30 7 0xc9 19 3 0x94 31 7 0xc8 18 3 0x93 32 6 0xc7 17 3 0x92 33 5 0xc6 16 4 0x91 34 5 0xc5 15 4 0x90 35 4 0xc4 14 4 0x8f 36 4 0xc3 13 5 0x8e 37 3 0xc2 12 5 0x8d 38 3 0xc1 11 5 0x8c 39 2 0xc0 10 5 0x8b 40 2 0xbf 9 6 0x8a 41 1 0xbe 8 6 0x89 4...

Page 197: ...ks TEMCLK 15 9 0x00 R 8 DBRUN 0 H0 R W 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W Bits 15 9 Reserved Bit 8 DBRUN This bit sets whether the TEM operating clock is supplied in DEBUG mode or not 1 R W Clock supplied in DEBUG mode 0 R W No clock supplied in DEBUG mode Bits 7 6 Reserved Bits 5 4 CLKDIV 1 0 These bits select the division ratio of the TEM operating clock Bits...

Page 198: ...lock is stopped TEM Conversion Result Register Register name Bit Bit name Initial Reset R W Remarks TEMRSLT 15 8 0x00 R 7 0 TEMP 7 0 0x00 H0 R Bits 15 8 Reserved Bits 7 0 TEMP 7 0 The temperature conversion results are stored in these bits Invalid data is read before the conversion has completed For correspondence between the read value and temperature see Table 20 4 3 1 TEM Interrupt Flag and Sta...

Page 199: ...pson Corporation 20 7 Rev 1 0 TEM Interrupt Enable Register Register name Bit Bit name Initial Reset R W Remarks TEMINTE 15 8 0x00 R 7 1 0x00 R 0 TEMIE 0 H0 R W Bits 15 1 Reserved Bit 0 TEMIE This bit enables TEM interrupts 1 R W Enable interrupts 0 R W Disable interrupts ...

Page 200: ...or Argument 2 Argument 1 Coprocessor output Flag output Operation result COPRO 1 1 COPRO Configuration Figure 21 Operation Mode and Output Mode 21 2 COPRO operates according to the operation mode specified by the application program As listed in Table 21 2 1 COPRO supports nine operations The multiplication division and MAC results are 32 bit data therefore the S1C17 Core cannot read them in one a...

Page 201: ...ed multiplication 0x5 Signed multiplication mode Performs signed multiplication 0x6 Reserved 0x7 Signed MAC mode Performs signed MAC operation 0x8 Unsigned division mode Performs unsigned division 0x9 Signed division mode Performs signed division 0xa 0xf Reserved Multiplication 21 3 The multiplication function performs A 32 bits B 16 bits C 16 bits The following shows a procedure to perform a mult...

Page 202: ...idue D 16 bits The following shows a procedure to perform a division 1 Set the mode to 0x08 unsigned division 16 low order bits output mode or 0x09 signed division 16 low order bits output mode 2 Send the 16 bit dividend B and 16 bit divisor C to COPRO using a ld ca instruction 3 Read the one half result 16 low order bits quotient and the flag status 4 Set the mode to 0x13 operation result read 16...

Page 203: ...x00 to COPRO with another instruc tion To load a 16 bit value to the operation result register Set the operation mode to 0x01 initialize mode 1 and then send the initial value 16 bits to COPRO using a ld cf instruction To load a 32 bit value to the operation result register Set the operation mode to 0x02 initialize mode 2 and then send the initial value 32 bits to COPRO using a ld cf instruction 2...

Page 204: ...res 31 0 rd res 15 0 psr CVZN 0b0100 if an overflow has oc curred Otherwise psr CVZN 0b0000 The operation result register keeps the operation result un til it is rewritten by other operation ext imm9 ld ca rd imm7 res 31 0 rd imm7 16 res 31 0 rd res 15 0 0x17 ld ca rd rs res 31 0 rd rs res 31 0 rd res 31 16 ext imm9 ld ca rd imm7 res 31 0 rd imm7 16 res 31 0 rd res 31 16 res operation result regis...

Page 205: ...ion is executed in an operation mode other than operation result read mode Reading Operation Results 21 6 The ld ca instruction cannot load a 32 bit operation result to a CPU register so a multiplication division or MAC operation returns the one half 16 bits according to the output mode result A 15 0 or A 31 16 and the flag status to the CPU registers Another one half should be read by setting COP...

Page 206: ... Tstg 65 to 125 C Recommended Operating Conditions 22 2 Item Symbol Condition Min Typ Max Unit Power supply voltage VDD 2 0 3 6 V Flash programming voltage VPP 7 3 7 5 7 7 V OSC1A oscillator oscillation frequency fOSC1A Crystal resonator 32 768 kHz OSC3A oscillator oscillation frequency fOSC3A Crystal or ceramic resonator 0 2 20 MHz EXOSC external clock frequency fEXOSC When supplied from an exter...

Page 207: ... normal mode 19 6 24 1 µA OSC1A 32 kHz OSC1B OFF OSC3A OFF OSC3B OFF SYSCLK OSC1A 2 executed on Flash 1 6 35 9 13 µA IRUN30 OSC1A 32 kHz OSC1B OFF OSC3A OFF OSC3B 20 MHz SYSCLK OSC3B executed on Flash 1 5 500 5 900 µA OSC1A 32 kHz OSC1B OFF OSC3A OFF OSC3B 8 MHz SYSCLK OSC3B 2 executed on Flash 1 1 620 1 710 µA IRUN40 OSC1A 32 kHz OSC1B OFF OSC3A 20 MHz OSC3B OFF SYSCLK OSC3A executed on Flash 1 5...

Page 208: ... 32 kHz OSC1B OFF OSC3A OFF OSC3B OFF Typ value Typ value 50 18 16 14 12 10 8 6 4 2 0 25 0 25 50 75 100 Ta C I HALT1 µA VDD 3 6 V VDD 2 0 V 50 1 8 1 6 1 4 1 2 1 0 0 8 0 6 0 4 0 2 0 25 0 25 50 75 100 Ta C I HALT2 µA VDD 3 6 V VDD 2 0 V Current consumption temperature characteristic Current consumption temperature characteristic in RUN mode OSC1B operation in RUN mode OSC1A operation OSC1A OFF OSC1B...

Page 209: ... 2 0 to 3 6 V VSS 0 V Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit High level Schmitt input threshold voltage VT 0 5 VDD 0 9 VDD V Low level Schmitt input threshold voltage VT 0 1 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV Input pull up resistance RIN 100 270 500 kW Pin capacitance CIN 15 pF Reset Low pulse width tSR 2 µs RESET tSR VT VT POR BOR characteristics Unless otherw...

Page 210: ...kHz Dependence of oscillation frequency on temperature 2 TfOSC1B Frequency accuracy per 1 C change in temperature with reference to 25 C 0 12 0 3 C 1 In chip mounting the value may exceed the range shown above according to the mount condition on the board 2 Reference value OSC1B oscillation frequency temperature characteristic Typ value 50 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 25 0 25 50 75 100 Ta C...

Page 211: ...Unless otherwise specified VDD 2 0 to 3 6 V VSS 0 V Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit EXOSC external clock duty ratio tEXOSCD tEXOSCD tEXOSCH tEXOSC 46 54 High level Schmitt input threshold voltage VT 0 5 VDD 0 9 VDD V Low level Schmitt input threshold voltage VT 0 1 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV EXOSC tEXOSCH tEXOSC 1 fEXOSC VT VT VT tEXOSCH tEXOSC 1...

Page 212: ...0 5 mA Low level output current IOL P00 07 P10 17 P20 27 P30 37 P40 41 PD0 D2 VOL 0 1 VDD 0 5 mA Leakage current ILEAK P00 07 P10 17 P20 27 P30 37 P40 41 PD0 D1 150 150 nA Input pull up resistance RINU P00 07 P10 17 P20 27 P30 37 P40 41 PD0 D1 75 150 300 kW Input pull down resistance RIND P00 07 P10 17 P20 27 P30 37 P40 41 PD0 D1 75 150 300 kW Pin capacitance CIN P00 07 P10 17 P20 27 P30 37 P40 41...

Page 213: ...76 3 100 3 224 V SVDCTL SVDC 4 0 bits 0x1a 3 072 3 200 3 328 V SVDCTL SVDC 4 0 bits 0x1b 3 168 3 300 3 432 V SVDCTL SVDC 4 0 bits 0x1c 3 264 3 400 3 536 V SVDCTL SVDC 4 0 bits 0x1d 3 360 3 500 3 640 V SVDCTL SVDC 4 0 bits 0x1e 3 456 3 600 3 744 V SVD circuit enable response time tSVDEN 1 500 µs SVD circuit response time tSVD 60 µs SVD circuit current ISVD SVDCTL SVDMD 1 0 bits 0x0 SVDCTL SVDC 4 0 ...

Page 214: ...m Symbol Condition Min Typ Max Unit SPICLKn cycle time tSCYC 500 ns SPICLKn High pulse width tSCKH 200 ns SPICLKn Low pulse width tSCKL 200 ns SDIn setup time tSDS 70 ns SDIn hold time tSDH 10 ns SDOn output delay time tSDO CL 30 pF 1 100 ns SPISSn setup time tSSS 70 ns SPISSn High pulse width tSSH 80 ns SDOn output start time tSDD CL 30 pF 1 100 ns SDOn output stop time tSDZ CL 30 pF 1 80 ns 1 CL...

Page 215: ... SCLn fall time tf 300 300 ns STOP condition setup time tSU STO 4 0 0 6 µs Bus free time tBUF 4 7 1 3 µs After this period the first clock pulse is generated SDAn SCLn S tf tBUF tHD STA 1 fSCL 1st clock cycle tf 9th clock cycle S START condition Sr Repeated START condition P STOP condition tr tHD DAT tHIGH tSU STA tLOW tr tSU DAT Sr P S tHD STA tSU STO Parallel Interface PIO Characteristics 22 12 ...

Page 216: ... capacitance CREF 100 pF Time base counter clock frequency fTCCLK 8 2 MHz High level Schmitt input threshold voltage VT 0 5 VDD 0 9 VDD V Low level Schmitt input threshold voltage VT 0 1 VDD 0 5 VDD V Schmitt input hysteresis voltage DVT 180 mV R F converter operating current IRFC CREF 1000 pF RREF RSEN 100 kW Ta 25 C DC oscillation mode 0 9 1 5 mA AC oscillation mode 2 3 5 mA 1 In this characteri...

Page 217: ...erature detection circuit current consumption Unless otherwise specified VDD 2 0 to 3 6 V VSS 0 V Ta 25 C Item Symbol Condition Min Typ Max Unit Temperature detection circuit operating current 1 ITEM 6 12 µA 1 This value is added to the current consumption during HALT execution with or without heavy load protection mode when the temperature detection circuit is active Temperature detection circuit...

Page 218: ...D VSS Electrolytic capacitor Place as closer to VDD pin 18 as possible CPW1 3 Capacitor between VDD VSS Ceramic capacitor Place as closer to VDD pin 18 as possible CPW2 VD1 stabilization capacitor Ceramic capacitor CPW3 VOSC stabilization capacitor Ceramic capacitor CPW4 6 Flash power supply voltage boosting capacitors Ceramic capacitor CPW7 VPP stabilization capacitor Ceramic capacitor RDBG DSIO ...

Page 219: ...ical Manual Seiko Epson Corporation 24 1 Rev 1 0 Package 24 TQFP13 64pin package Unit mm 10 12 33 48 10 12 17 32 INDEX 0 17 0 27 16 1 64 49 1 0 1 1 2 max 1 0 3 0 75 0 10 0 09 0 2 0 5 1 TQFP13 64pin Package Dimensions Figure 24 ...

Page 220: ... 0x00 H0 R WP 0x4008 MSCPSR MISC PSR Register 15 8 0x00 R 7 5 PSRIL 2 0 0x0 H0 R 4 PSRIE 0 H0 R 3 PSRC 0 H0 R 2 PSRV 0 H0 R 1 PSRZ 0 H0 R 0 PSRN 0 H0 R 0x4020 Power Generator PWG Address Register name Bit Bit name Initial Reset R W Remarks 0x4020 PWGVD1CTL PWG VD1 Regulator Control Register 15 8 0x00 R 7 2 0x00 R 1 0 REGMODE 1 0 0x0 H0 R WP 0x4040 0x404e Clock Generator CLG Address Register name B...

Page 221: ...2 OSC3ASTAIE 0 H0 R W 1 OSC1STAIE 0 H0 R W 0 OSC3BSTAIE 0 H0 R W 0x404e CLGFOUT CLG FOUT Control Register 15 8 0x00 R 7 0 R 6 4 FOUTDIV 2 0 0x0 H0 R W 3 2 FOUTSRC 1 0 0x0 H0 R W 1 0 R 0 FOUTEN 0 H0 R W 0x4052 Theoretical Regulation TR Address Register name Bit Bit name Initial Reset R W Remarks 0x4052 TRCTL Theoretical Regulation Control Register 15 10 0x00 R 9 REGFREQ 0 H0 R W 8 REGMONEN 0 H0 R W...

Page 222: ... 6 15 11 0x00 R 10 8 ILV13 2 0 0x0 H0 R W SPI Ch 2 interrupt ILVSPI_2 7 3 0x00 R 2 0 ILV12 2 0 0x0 H0 R W 16 bit timer Ch 3 interrupt ILVT16_3 0x408e ITCLV7 ITC Interrupt Level Setup Register 7 15 11 0x00 R 10 8 ILV15 2 0 0x0 H0 R W 16 bit PWM timer Ch 1 interrupt ILVT16A3_1 7 3 0x00 R 2 0 ILV14 2 0 0x0 H0 R W 16 bit PWM timer Ch 0 interrupt ILVT16A3_0 0x4090 ITCLV8 ITC Interrupt Level Setup Regis...

Page 223: ...W Cleared by writing 1 8 HDIF 0 H0 R W 7 1HIF 0 H0 R W 6 10MIF 0 H0 R W 5 1MIF 0 H0 R W 4 10SIF 0 H0 R W 3 1HZIF 0 H0 R W 2 4HZIF 0 H0 R W 1 8HZIF 0 H0 R W 0 32HZIF 0 H0 R W 0x40c6 RTCMIN RTC Minute Second Register 15 0 R 14 8 RTCMIN 6 0 x R W 7 0 R 6 0 RTCSEC 6 0 x R W 0x40c8 RTCHUR RTC Hour Register 15 8 0x00 R 7 AMPM x R W 6 0 R 5 0 RTCHUR 5 0 x R W 0x4100 0x4106 Supply Voltage Detector SVD Add...

Page 224: ... R W 7 2 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x4166 T16_0TR T16 Ch 0 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x4168 T16_0TC T16 Ch 0 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x416a T16_0INTF T16 Ch 0 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x416c T16_0INTE T16 Ch 0 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x41b...

Page 225: ... 15 8 P1OUT 7 0 0x00 H0 R W 7 0 P1IN 7 0 x H0 R 0x4212 P1IOEN P1 Port Enable Register 15 8 P1IEN 7 0 0x00 H0 R W 7 0 P1OEN 7 0 0x00 H0 R W 0x4214 P1RCTL P1 Port Pull up down Control Register 15 8 P1PDPU 7 0 0x00 H0 R W 7 0 P1REN 7 0 0x00 H0 R W 0x4216 P1INTF P1 Port Interrupt Flag Register 15 8 0x00 R 7 0 P1IF 7 0 0x00 H0 R W Cleared by writing 1 0x4218 P1INTCTL P1 Port Interrupt Control Register ...

Page 226: ...15 8 P3PDPU 7 0 0x00 H0 R W 7 0 P3REN 7 0 0x00 H0 R W 0x423c P3MODSEL P3 Port Mode Select Register 15 8 0x00 R 7 0 P3SEL 7 0 0x00 H0 R W 0x423e P3FNCSEL P3 Port Function Select Register 15 14 P37MUX 1 0 0x0 H0 R 13 12 P36MUX 1 0 0x0 H0 R W 11 10 P35MUX 1 0 0x0 H0 R W 9 8 P34MUX 1 0 0x0 H0 R W 7 6 P33MUX 1 0 0x0 H0 R W 5 4 P32MUX 1 0 0x0 H0 R W 3 2 P31MUX 1 0 0x0 H0 R W 1 0 P30MUX 1 0 0x0 H0 R W 0x...

Page 227: ...UN 0 H0 R WP 7 4 CLKDIV 3 0 0x0 H0 R WP 3 2 KRSTCFG 1 0 0x0 H0 R WP 1 0 CLKSRC 1 0 0x0 H0 R WP 0x42e2 PINTFGRP P Port Interrupt Flag Group Register 15 8 0x00 R 7 2 0x00 R 1 P1INT 0 H0 R 0 P0INT 0 H0 R 0x4380 0x438e UART UART Address Register name Bit Bit name Initial Reset R W Remarks 0x4380 UA0CLK UART Ch 0 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 6 0x0 R 5 4 CLKDIV 1 0 0x0 H0 R W 3 ...

Page 228: ...able Register 15 8 0x00 R 7 0 R 6 TENDIE 0 H0 R W 5 FEIE 0 H0 R W 4 PEIE 0 H0 R W 3 OEIE 0 H0 R W 2 RB2FIE 0 H0 R W 1 RB1FIE 0 H0 R W 0 TBEIE 0 H0 R W 0x43a0 0x43ac 16 bit Timer T16 Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x43a0 T16_1CLK T16 Ch 1 Clock Control Register 15 9 0x00 R 8 DBRUN 0 H0 R W 7 4 CLKDIV 3 0 0x0 H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x43a2 T16_1M...

Page 229: ...I Ch 0 Interrupt Flag Register 15 8 0x00 R 7 4 0x0 R 3 BSY 0 H0 R 2 TENDIF 0 H0 S0 R W Cleared by writing 1 1 RBFIF 0 H0 S0 R Cleared by reading the SPI0RXD register 0 TBEIF 1 H0 S0 R Cleared by writing to the SPI0TXD register 0x43ba SPI0INTE SPI Ch 0 Interrupt Enable Register 15 8 0x00 R 7 3 0x00 R 2 TENDIE 0 H0 R W 1 RBFIE 0 H0 R W 0 TBEIE 0 H0 R W 0x43c0 0x43d2 I2C I2C Address Register name Bit...

Page 230: ...1 6 GCIF 0 H0 S0 R W 5 NACKIF 0 H0 S0 R W 4 STOPIF 0 H0 S0 R W 3 STARTIF 0 H0 S0 R W 2 ERRIF 0 H0 S0 R W 1 RBFIF 0 H0 S0 R Cleared by reading the I2C0RXD register 0 TBEIF 0 H0 S0 R Cleared by writing to the I2C0TXD register 0x43d2 I2C0INTE I2C Ch 0 Interrupt Enable Register 15 8 0x00 R 7 BYTEENDIE 0 H0 R W 6 GCIE 0 H0 R W 5 NACKIE 0 H0 R W 4 STOPIE 0 H0 R W 3 STARTIE 0 H0 R W 2 ERRIE 0 H0 R W 1 RB...

Page 231: ...0INTF T16A3 Ch 0 Interrupt Flag Register 15 8 0x00 R 7 6 0x0 R 5 CAPBOWIF 0 H0 R W Cleared by writing 1 4 CAPAOWIF 0 H0 R W 3 CAPBIF 0 H0 R W 2 CAPAIF 0 H0 R W 1 CMPBIF 0 H0 R W 0 CMPAIF 0 H0 R W 0x500e T16A0INTE T16A3 Ch 0 Interrupt Enable Register 15 8 0x00 R 7 6 0x0 R 5 CAPBOWIE 0 H0 R W 4 CAPAOWIE 0 H0 R W 3 CAPBIE 0 H0 R W 2 CAPAIE 0 H0 R W 1 CMPBIE 0 H0 R W 0 CMPAIE 0 H0 R W 0x5020 0x502e 16...

Page 232: ...x00 R 7 6 0x0 R 5 CAPBOWIF 0 H0 R W Cleared by writing 1 4 CAPAOWIF 0 H0 R W 3 CAPBIF 0 H0 R W 2 CAPAIF 0 H0 R W 1 CMPBIF 0 H0 R W 0 CMPAIF 0 H0 R W 0x502e T16A1INTE T16A3 Ch 1 Interrupt Enable Register 15 8 0x00 R 7 6 0x0 R 5 CAPBOWIE 0 H0 R W 4 CAPAOWIE 0 H0 R W 3 CAPBIE 0 H0 R W 2 CAPAIE 0 H0 R W 1 CMPBIE 0 H0 R W 0 CMPAIE 0 H0 R W 0x5180 0x5186 Clock Timer CT Address Register name Bit Bit name...

Page 233: ...rrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x526c T16_2INTE T16 Ch 2 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x5270 0x527a SPI SPI Ch 1 Address Register name Bit Bit name Initial Reset R W Remarks 0x5270 SPI1MOD SPI Ch 1 Mode Register 15 8 0x00 R 7 6 0x0 R 5 PUEN 0 H0 R W 4 NOCLKDIV 0 H0 R W 3 LSBFST 0 H0 R W 2 CPHA 0 H0 R W 1 CPOL 0 H0...

Page 234: ... 0x00 R 1 PRESET 0 H0 R W 0 MODEN 0 H0 R W 0x5286 T16_3TR T16 Ch 3 Reload Data Register 15 0 TR 15 0 0xffff H0 R W 0x5288 T16_3TC T16 Ch 3 Counter Data Register 15 0 TC 15 0 0xffff H0 R 0x528a T16_3INTF T16 Ch 3 Interrupt Flag Register 15 8 0x00 R 7 1 0x00 R 0 UFIF 0 H0 R W Cleared by writing 1 0x528c T16_3INTE T16 Ch 3 Interrupt Enable Register 15 8 0x00 R 7 1 0x00 R 0 UFIE 0 H0 R W 0x5290 0x529a...

Page 235: ...H0 R W 3 2 0x0 R 1 0 CLKSRC 1 0 0x0 H0 R W 0x52e2 PIOMOD PIO Mode Register 15 8 0x00 R 7 2 0x00 R 1 PUL 0 H0 R W 0 GPIOMD 0 H0 R W 0x52e4 PIOCTL PIO Control Register 15 9 0x00 R 8 RACC 0 H0 W Always read as 0 7 2 0x00 R 1 SFTRST 0 H0 W Always read as 0 0 MODEN 0 H0 R W 0x52e6 PIOWRDAT PIO Address Write Data Register 15 8 PADDR 7 0 0x00 H0 R W 7 0 PWDATA 7 0 0x00 H0 R W 0x52e8 PIORDDAT PIO Read Dat...

Page 236: ... 15 8 0x00 R 7 3 0x00 R 2 SSENB 0 H0 R W 1 SSENA 0 H0 R W 0 SREF 0 H0 R W 0x5446 RFC0MCL RFC Ch 0 Measure ment Counter Low Register 15 0 MC 15 0 0x0000 H0 R W 0x5448 RFC0MCH RFC Ch 0 Measure ment Counter High Register 15 8 0x00 R 7 0 MC 23 16 0x00 H0 R W 0x544a RFC0TCL RFC Ch 0 Time Base Counter Low Regis ter 15 0 TC 15 0 0x0000 H0 R W 0x544c RFC0TCH RFC Ch 0 Time Base Counter High Regis ter 15 8 ...

Page 237: ... 15 8 0x00 R 7 3 0x00 R 2 SSENB 0 H0 R W 1 SSENA 0 H0 R W 0 SREF 0 H0 R W 0x5466 RFC1MCL RFC Ch 1 Measure ment Counter Low Register 15 0 MC 15 0 0x0000 H0 R W 0x5468 RFC1MCH RFC Ch 1 Measure ment Counter High Register 15 8 0x00 R 7 0 MC 23 16 0x00 H0 R W 0x546a RFC1TCL RFC Ch 1 Time Base Counter Low Regis ter 15 0 TC 15 0 0x0000 H0 R W 0x546c RFC1TCH RFC Ch 1 Time Base Counter High Regis ter 15 8 ...

Page 238: ... 0 CVTM 7 0 0x00 H0 R W 0x54c4 TEMCTL TEM Control Register 15 8 0x00 R 7 2 0x00 R 1 TEMTRG 0 H0 W Always read as 0 0 MODEN 0 H0 R W 0x54c6 TEMRSLT TEM Conversion Result Register 15 8 0x00 R 7 0 TEMP 7 0 0x00 H0 R 0x54c8 TEMINTF TEM Interrupt Flag and Status Register 15 8 0x00 R 7 5 0x0 R 4 TEMST 0 H0 R 3 1 0x0 R 0 TEMIF 0 H0 R W Cleared by reading the TEMRSLT register 0x54ca TEMINTE TEM Interrupt ...

Page 239: ...the slp instruction CLGOSC xxxxSLPC bits of the clock generator Setting the CLGOSC OSC3BSLPC OSC3ASLPC OSC1SLPC or EXOSCSLPC bit of the clock generator to 0 disables the oscillator circuit stop control when the slp instruction is executed To stop the oscillator circuits during SLEEP mode set these bits to 1 MODEN bits of the peripheral circuits Setting the MODEN bit of each peripheral circuit to 1...

Page 240: ...r Power Saving Methods B 2 Supply voltage detector configuration Continuous operation mode SVDCTL SVDMD 1 0 bits 0x0 always detects the power supply voltage therefore it increases current consumption Set the supply voltage detector to intermittent operation mode or turn it on only when required ...

Page 241: ...t circuit board layers Layers wired should be adequately shielded as shown to the right Fully ground adja cent layers where possible At minimum shield the area at least 5 mm around the above pins and wiring Even after implementing these precautions avoid configuring digital signal lines in parallel as described in 2 above Avoid crossing even on discrete layers except for lines carrying signals wit...

Page 242: ...f opening the package If the IC chip must be stored before mounting take measures to ensure light shielding 5 Adequate evaluations are required to assess nonvolatile memory data retention characteristics before prod uct delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting processes Unused pins 1 I O port P pins Unused pins should be left open The ...

Page 243: ...e I O port pins within the initialization routine when the debug functions are not used For details of the pin functions and the function switch control see the I O Ports chapter Note Do not perform the function switching shown above when the application is under development as the debug functions must be used The debugging cannot be performed after the pin function is switched The above processin...

Page 244: ..._handler 0x0c 0x30 I2C long ct_handler 0x0d 0x34 CT long t16_2_handler 0x0e 0x38 T16 ch2 long spi_1_handler 0x0f 0x3c SPI ch1 long t16_3_handler 0x10 0x40 T16 ch3 long spi_2_handler 0x11 0x44 SPI ch2 long t16a3_0_handler 0x12 0x48 T16A3 ch0 long t16a3_1_handler 0x13 0x4c T16A3 ch1 long rfc_0_handler 0x14 0x50 RFC ch0 long rfc_1_handler 0x15 0x54 RFC ch1 long epd_tcon_handler 0x16 0x58 EPD Tcon lon...

Page 245: ...nmi_handler 1 A rodata section is declared to locate the vector table in the vector section 2 Interrupt handler routine addresses are defined as vectors intXX_handler can be used for software interrupts 3 The program code is written in the text section 4 Sets the stack pointer 5 Sets the number of Flash memory read cycles See the Memory and Bus chapter ...

Page 246: ...REVISION HISTORY Revision History Code No Page Contents 412486300 All New establishment ...

Page 247: ...Shenzhen 518057 CHINA Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 0...

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