
21 Multiplier/Divider (COPRO)
21-6
Seiko epson Corporation
S1C17F13 TeChniCal Manual
(Rev. 1.0)
5.3 Conditions to Set the Overflow (V) Flag
Table 21.
Mode setting value
Sign of multiplication result Sign of operation result reg-
ister value
Sign of multiplication & ac-
cumulation result
0x07
0 (positive)
0 (positive)
1 (negative)
0x07
1 (negative)
1 (negative)
0 (positive)
An overflow occurs when a MAC operation performs addition of positive values and a negative value results, or
it performs addition of negative values and a positive value results. The coprocessor holds the operation result
until the overflow (V) flag is cleared.
Conditions to clear the overflow (V) flag
The overflow (V) flag that has been set will be cleared when an overflow has not been occurred during execu-
tion of the “
ld.ca
” instruction for MAC operation or when the “
ld.ca
” or “
ld.cf
” instruction is executed
in an operation mode other than operation result read mode.
Reading Operation Results
21.6
The “
ld.ca
” instruction cannot load a 32-bit operation result to a CPU register, so a multiplication, division or
MAC operation returns the one-half (16 bits according to the output mode) result (A[15:0] or A[31:16]) and the flag
status to the CPU registers. Another one-half should be read by setting COPRO into operation result read mode.
The operation result register keeps the loaded operation result until it is rewritten by other operation.
Operation result
register
Selector
S1C17 Core
COPRO
Argument 2
Argument 1
Coprocessor
output (16 bits)
Flag output
6.1 Data Path in Operation Result Read Mode
Figure 21.
6.1 Operation in Operation Result Read Mode
Table 21.
Mode set-
ting value
Instruction
Operations
Flags
Remarks
0x03
ld.ca %rd,%rs
%rd
←
res[15:0]
psr (CVZN)
←
0b0000 This operation mode does not
affect the operation result reg-
ister.
ld.ca %rd,
imm7
%rd
←
res[15:0]
0x13
ld.ca %rd,%rs
%rd
←
res[31:16]
ld.ca %rd,
imm7
%rd
←
res[31:16]
res: operation result register