Epson EPL-N2000, Service Manual

Page: 157 / 188

Table A-16 C207 MAIN Board CN5 (I/O Bus)
Pin Signal Name I/O Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41~60
PCLK
RST
GND
GND
GND
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
AB0
AB1
AB2
AB3
AB4
CS
RD
WR
IREQ
NMI
DREQ
DTCT
+5V
+5V
+5V
+5V
TXD+
TXD-
RXD+
RXD-
DTR
CTS
NC
NC
LCD
SWRD
Not used
I
I/O
-
-
-
-
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
-
-
-
-
-
-
O
O
O
O
-
-
-
-
O
O
I
I
O
I
-
-
I
I
-
System clock for 85230-10
Reset signal
GND
GND
GND
GND
Bidirectional data bus 0
Bidirectional data bus 1
Bidirectional data bus 2
Bidirectional data bus 3
Bidirectional data bus 4
Bidirectional data bus 5
Bidirectional data bus 6
Bidirectional data bus 7
Address bus
Address bus
Address bus
Address bus
Address bus
Chip select signal
Read signal. Goes LOW with WR signal at reset.
Write signal. Goes LOW with RD signal at reset.
Interruption request signal
Non-maskable interrupt request signal
DMA request signal
Board detection signal
+5 V
+5 V
+5 V
+5 V
Not used
Not used
Not used
Not used
Not used
Not used
No connection
No connection
Not used
Not used
—
Appendix EPL-N2000 Service Manual
A-8 Rev. A