APPENDIX
REV.-A
CPU Timing
Refer to Figures A-3 through A-5 for CPU timing diagrams. Three oscillations define one state. The OP code
fetch requires four states. During T1 to T3, program memory is read, and instructions are interpreted during
T4. Address bus lines 15-8 are output from T1 to T4. Address bus lines 7-0 (PD7-0) are used in the multiplex
mode. The address is latched during T1 at the ALE signal.
Since the memory addressed is enabled after disengaging the driver (AD7-0), RD is output from T1-T3, fet-
ched at T3, and processed internally at T4. The ALE and RD signals are executed from T1-T3, and the OP
code fetch for these two signals is performed at T4. The WR signal is output from the middle of T1 to the
beginning of T3. The address and ALE timing is the same as that for memory read; however, following
address output, AD7-0 (PD7-0) are not disabled, and write data is output at AD7-0 at the beginning of T1
and at the end of T3.
NOTE:
When PD7-0 are set to the multiplexed address/data bus (AD7-0) and PF7-0 to the address bus
(AB7-0), the RD and WR signals in the machine cycle are HIGH when memory is not being accessed.
I
T1
T2
T3
T4
CLOCK
ALE
A B 1 5 - 8
(PF7 - 0)
Y
ADDRESS
X
AD7-0
(PD7
-
0)
A D D R E S S
OP
CODE
Figure A-3. OP Code Fetch Timing
CLOCK
A B 1 5 - 8
(PF7 - 0)
X
ADDRESS
X
A D 7 - 0
(PD7 -0)
ADDRESS
READ DATA
Figure A-4. Memory Read Timing
CLOCK
ALE
A B 1 5 - 8
(PF7 - 0)
X
ADDRESS
X
A D 7 - 0
(PD7 - 0)
ADDRESS
WRITE DATA
X
Figure A-5. Memory Write Timing
A-6
LQ-510
Summary of Contents for AP-4000
Page 1: ...LQ 510 AP 4000 T E C H N I C A L M A N U A L EPSON ...
Page 4: ...REV A REVISION SHEET iv LQ 510 ...
Page 103: ...REV A PRINCIPLES OF OPERATION LQ 510 Figure 2 68 A D Converter Circuit 2 61 ...
Page 125: ...OPTIONAL EQUIPMENT REV A 3 16 Figure 3 12 Lubrication Points 2 LQ 510 ...
Page 167: ......
Page 192: ...MAINTENANCE REV A L __ w w n Figure 6 3 LQ 510 Lubrication Points 6 3 LQ 510 ...
Page 202: ...APPENDIX REV A Table A 6 E01A05 Pin Functions A 8 LQ 510 ...
Page 212: ...3 L CN 1 ...
Page 213: ...REV A APPENDIX Figure A 25 SANPSE Board Component Layout LQ 510 A 19 ...
Page 214: ...REV A APPENDIX J Figure A 26 SANPSE Board Circuit Diagram A 20 LQ 510 ...
Page 215: ...REV A APPENDIX Figure A 27 SANPNL W Board Circuit Diagram LQ 510 A 21 ...
Page 216: ... w 3 0 4 CN1 14 18 22 I IP I9 3 1 2LSl39 2 6 8 2 4 9 TOM4 BOARD Y 4 5 4 2 0 9 0 0 0 0 0 ...
Page 220: ...h i ...
Page 221: ...REV A APPENDIX 506 Figure 14 32 Model 5710 Printer Mechanism Exploded Diagram A 29 ...
Page 222: ...APPENDIX REV A Figure A 33 C80006 Pull Tractor Exploded Diagram A 30 LQ 510 ...
Page 223: ... Y ...
Page 224: ...APPENDIX REV Figure A 35 LQ 510 Printer Cover A Case Outline Drawing A 32 LQ 510 ...
Page 225: ...APPENDIX REV A J 2 7 J Bl Figure A 36 LQ 510 Printer Cover B Case Outline Drawing LQ 510 A 33 ...
