REV.-A
APPENDIX
Table A-5. µPD7810/7811 Port Functions
Pins
Signal
1-8
PA0-7
9-16
PB0-7
17-24
PC0-7
25
NMI
26
INT 1
27, 29
MODE1,0
28
RESET
30, 31
X2, X1
32
Vss
33
AVss
34-41
AN0-7
42
VAref
43
AVcc
44
R D
Direction
In/Out
In/Out
In/Out
In
In
In/Out
In
-
-
-
In
In
-
out
Descriptions
Port A: 8-bit l/O with output latch. l/O possible with mode A
(MA) register. Output HIGH.
Port B: 8-bit I/O with output latch. l/O possible with mode B
(MB) register. Output HIGH.
Port C: 8-bit l/O with output latch. Port control mode can be
set by mode control C (MCC) register. Output HIGH.
Non-maskable interrupt of the edge trigger (trailing edge).
Maskable interrupt input of the edge trigger (leading edge).
Also used as the AC input zero cross detecting terminal.
7611: 0 = LOW and 1 = HIGH.
7810 modes set according to external memory (see Table A-2).
LOW reset.
Crystal connection for built-in clock pulse. When clock pulses
are supplied externally, input must be to Xl.
Supply voltage, Vss, 0V.
Analog Vss.
8 analog inputs of the A/D converter. AN7-4 can be used as
the input terminals to detect the leading edge and to set the
test flag upon detection of the trailing edge.
Reference voltage.
Analog Vcc.
Read strobe. LOW at the read machine cycle and at reset,
HIGH at other times.
45
WR
out
Write strobe. LOW during the write machine cycle and at reset,
HIGH at other times.
46
ALE
out
Address latch enable. Latches the lower B address bits to ac-
cess external memory.
47-54
PF0-7
55-62
PD0-7
Port F:
7611: Port bit-by-bit l/O possible by mode F register. In exten-
sion mode gradual address output assignment is possible in
accordance with the size of external memory. See Table A-3.
7810: By setting mode 0 and 1, assignment to the address bus
(AB15-8) can be made in accordance with the size of the exter-
nal memory. The remaining terminals can be used as l/O
ports. See Table A-4.
Port D:
7811: Port bit-by-bit l/O possible. In extension mode, PD7-0
acts as the multiplexed address/data bus (AD7-0).
7810: Multiplexed address/data bus to access external
memory.
63
V
D D
64
Vcc
-
Supply voltage, V
DD
+5 V.
-
Supply voltage, VCC +5 V.
LQ-510
A-5
Summary of Contents for AP-4000
Page 1: ...LQ 510 AP 4000 T E C H N I C A L M A N U A L EPSON ...
Page 4: ...REV A REVISION SHEET iv LQ 510 ...
Page 103: ...REV A PRINCIPLES OF OPERATION LQ 510 Figure 2 68 A D Converter Circuit 2 61 ...
Page 125: ...OPTIONAL EQUIPMENT REV A 3 16 Figure 3 12 Lubrication Points 2 LQ 510 ...
Page 167: ......
Page 192: ...MAINTENANCE REV A L __ w w n Figure 6 3 LQ 510 Lubrication Points 6 3 LQ 510 ...
Page 202: ...APPENDIX REV A Table A 6 E01A05 Pin Functions A 8 LQ 510 ...
Page 212: ...3 L CN 1 ...
Page 213: ...REV A APPENDIX Figure A 25 SANPSE Board Component Layout LQ 510 A 19 ...
Page 214: ...REV A APPENDIX J Figure A 26 SANPSE Board Circuit Diagram A 20 LQ 510 ...
Page 215: ...REV A APPENDIX Figure A 27 SANPNL W Board Circuit Diagram LQ 510 A 21 ...
Page 216: ... w 3 0 4 CN1 14 18 22 I IP I9 3 1 2LSl39 2 6 8 2 4 9 TOM4 BOARD Y 4 5 4 2 0 9 0 0 0 0 0 ...
Page 220: ...h i ...
Page 221: ...REV A APPENDIX 506 Figure 14 32 Model 5710 Printer Mechanism Exploded Diagram A 29 ...
Page 222: ...APPENDIX REV A Figure A 33 C80006 Pull Tractor Exploded Diagram A 30 LQ 510 ...
Page 223: ... Y ...
Page 224: ...APPENDIX REV Figure A 35 LQ 510 Printer Cover A Case Outline Drawing A 32 LQ 510 ...
Page 225: ...APPENDIX REV A J 2 7 J Bl Figure A 36 LQ 510 Printer Cover B Case Outline Drawing LQ 510 A 33 ...
