EPOX mu-3vsa, User Manual

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BIOS
Page 4-8
SDRAM Cycle length : This setting defines the CAS timing parameter of the
SDRAM in terms of clocks. Default is by SPD.
2 : Provides faster memory performance.
3 : Provides better memory compatibility.
Bank Interleave: The item allows you to set how many banks of SDRAM support
in your mainboard. Default is by SPD.
The Choice: 2 Bank, 4 Bank, Disabled.
Memory Hole : You can reserve this memory area for the use of ISA adaptor
ROMs. The default is Disabled.
Enabled : This field enables the main memory (15~16MB) to remap to ISA BUS.
Disabled : Normal Setting.
Note: If this feature is enabled you will not be able to cache this memory segment.
P2C/C2P Concurrency : This item allows you to enable/disable the PCI to CPU,
CPU to PCI concurrency.
System BIOS Cacheable : This allows you to copy your BIOS code from slow
ROM to fast RAM. The default is Disabled.
Enabled : The option will improve system performance. However, if any program
writes to this memory area, a system error may result.
Disabled : System BIOS non-cacheable.
Video BIOS Cacheable : This option copies the video ROM BIOS to fast RAM
(C0000h to C7FFFh). The default is Enabled.
Enabled : Enables the Video BIOS Cacheable to speed up the VGA Performance.
Disabled : Will not use the Video BIOS Cacheable function.
Video RAM Cacheable : This option allows the CPU to cache read/writes of the
video RAM. The default is Enabled.
Enabled : This option allows for faster video access.
Disabled : Reduced video performance.
AGP Aperture Size : The amount of system memory that the AGP card is
allowed to share. The default is 64.