EPOX mu-3vsa, User Manual

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BIOS
Page 4-7
DRAM Timing By SPD : Select Enabled for setting SDRAM timing by SPD.
The Choice: Enabled, Disabled.
DRAM Clock : The item will synchronize/asynchronize DRAM clock operation.
Host CLK: Sets the memory to run at the same speed with the processor’s
front side bus. If you have CPU at 133MHz FSB & PC133
memory, please use this selection.
HCLK+ 33M: Sets the memory to run at 33MHz faster than the processor’s front
side bus. We recommend to select this item while your CPU is
running at 100MHz FSB and memory is PC133 specification to
optimize your system performance.
HCLK - 33M: Sets the memory to run at 33MHz slower than the processor’s
front side bus. This selection is suggested to be used under CPU
at 133MHz FSB and PC100 memory configuration.
4-3 Advanced Chipset Features
Choose the “CHIPSET FEATURES SETUP” in the CMOS SETUP UTILITY menu
to display following menu.
Figure 4: Chipset Features Setup