BIOS
Page 4-6
SLI Broadcast Aperture
This item allows you select the SLI broadest aperture for faster execution.
Options: Auto, Disabled.
LDT Frequency
This item allows you select the Hyper Transport Frequency linking the chipsets.
Options: 1x, 2x, 3x, 4x, 5x. (1x-->200MHz, 2x-->400MHz, 3x-->600MHz, 4x-->800MHz,
5x-->1000MHz)
Video BIOS Cacheable
This item allows the video BIOS to be cached in memory for faster execution.
Options: Disabled, Enabled.
Performance Options
Scroll to Performance Options and press <Enter>. The following screen appears:
Memory Timings
For setting DRAM timing, select “Expert” to enter timings manually.
Options: Optimal, Expert.
T(CAS)
This item specifies the number of clock cycles needed after a Column Address Strobe
(CAS) signal before data can be read.
Options: Auto, 1 ~ 6.
T(RCD)
This field specifies the RAS# to CAS# delay to read/write command to the same bank.
Options: Auto, 1 ~ 7.
T(RP)
This field specifies the Row Precharge Time. Precharge to active or Auto-refresh of
the same bank.
Options: Auto, 1 ~ 7.
Summary of Contents for EP-5NVA+SLI
Page 6: ...vi Page Left Blank...
Page 12: ...Introduction Page 1 6 1 3 System Block Diagram...
Page 76: ...Appendix B 4...
