EPOX EP-3WDF2, Manual

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Introduction EP-3WEF2/3WDF2
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applied to the needs of a wide diversity of multimedia and communications
applications. The highlights of the technology are:
* Single Instruction, Multiple Data (SIMD) technique
* 57 new instructions
* Eight 64-bit wide MMX technology registers
* Four new data types
Intel Coppermine processors (FC-PGA) 370
These Coppermine-128K and Coppermine-256K processor is the next addition to the
P6 micro architecture product family. The FC-PGA package is a new addition to the
Intel IA-32 processor line and hereafter will be referred to as the “Coppermine FC-
PGA processor”, or simply “The processor”. The package utilizes the same 370-pin
zero insertion force socket (PGA370) used by the Intel Celeron processor. Thermal
solutions are attached directly to the back of the processor core package without the
use of a thermal plate or heat spreader.
The Coppermine processor, like the Intel Celeron, Intel Pentium II and Pentium III in
the P6 family processor, implement a Dynamic Execution micro architecture --- a unique
combination of multiple branch prediction, data flow analysis, and speculative
execution. This enable these processors to deliver higher performance than the Intel
Pentium processor, while maintaining binary compatibility with all previous Intel Ar-
chitecture processors. The processor also executes Intel MMX technology instruc-
tions for enhanced media and communication performance just as it’s predecessor the
Intel Pentium III processor. Additionally the Coppermine FC-PGA processor executes
streaming SIMD (Single-Instruction Multiple Data) Extensions for enhanced floating
point and 3-D application performance. The concept of processor identification, via
CPUID, is extended in the processor family with the addition of a processor serial
number. The processor utilizes multiple low-power states such as AutoHALT, Stop-
Grant, Sleep and Deep Sleep to conserve power during idle times.
The processor includes an integrated on-die, 128KB or 256KB, 8-way set associative
level-two (L2) cache with a separated 16KB level one (L1) instruction cache and 16KB
level one (L1) data cache. These cache arrays run at the full speed of the processor