EPOX EP-3WDF2, Manual

Page: 42 / 83

BIOS EP-3WEF2/3WDF2
Page 4-12
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transac-
tions cycles. Select
Enabled to support compliance with PCI specification
version 2.1.
The Choice: Enabled, Disabled.
On-Chip Video Window Size
The amount of system memory that the 810 series AGP is allowed to share. The
default is 64.
32: 32MB of systems memory accessable by the 810 series AGP.
64: 64MB of systems memory accessable by the 810 series AGP.
Onboard Display Cache Setting
(Optional for 82810-DC100 and 82810E)
Setting the onboard display cache timing.
CAS # Latency
Select the local memory clock periods.
The Choice: 2, 3
Paging Mode Control
Select the paging mode control.
The Choice: Close, Open.
RAS-to-CAS Override
Select the display cache clock periods control.
The Choice: by CAS# LT, Override(2).
RAS# Timing
This item controls RAS# active to Protegra, and refresh to RAS# active delay ( in
local memory clocks).
The Choice: Fast, Slow.
RAS# Precharge Timing
This item controls RAS# precharge (in local memory clocks).
The choice: Fast, Slow.
Local Memory Frequency
Select 4M Local Memory Frequency of 100MHz or 133MHz. This item for 3WEF2
Model only.
The choice: 100, 133, Auto.