Energy micro EFM32-G8XX-DK, User Manual

Page: 54 / 70

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Control MCU Power & Bypass
J-Link LED Debug LED
FSMC_D12 CTRLMCU_DATA12
FSMC_D11 CTRLMCU_DATA11
FSMC_D10 CTRLMCU_DATA10
FSMC_D9 CTRLMCU_DATA9
FSMC_D8 CTRLMCU_DATA8
FSMC_D7 CTRLMCU_DATA7
FSMC_D6 CTRLMCU_DATA6
FSMC_D4 CTRLMCU_DATA4
FSMC_D5 CTRLMCU_DATA5
FSMC_D13 CTRLMCU_DATA13
FSMC_D14 CTRLMCU_DATA14
FSMC_D15 CTRLMCU_DATA15
FSMC_D2 CTRLMCU_DATA2
FSMC_D3 CTRLMCU_DATA3
FSMC_#OE
FSMC_#W E
FSMC_#W AIT
FSMC_#E1
FSMC_CLK
FSMC_D0 CTRLMCU_DATA0
FSMC_D1 CTRLMCU_DATA1
CTRLMCU_ADDR19 FPGA_CFG_#CS
CTRLMCU_ADDR20 FPGA_CFG_RD#W R
CTRLMCU_ADDR21 FPGA_CFG_#INIT
CTRLMCU_ADDR16
CTRLMCU_ADDR17
CTRLMCU_ADDR18
GND
GND
GND
3V3 3V3
GND GND
GND
GND
GND
GND
GND
GND
3V3
3V3
ADC_VREF
GND
3V3
3V3
3V3
3V3 3V3
3V3 3V3
3V3
3V3
3V3
CTRLMCU_DATA[15..0] (p 7,9)
CTRLMCU_SPI_MISO (p 11)
FPGA_CFG_#PROG (p 10)
CTRLMCU_FSMC_CLK (p 7)
CTRLMCU_FSMC_#OE (p 9)
CTRLMCU_FSMC_#W E (p 9)
CTRLMCU_FSMC_#E1 (p 9)
CTRLMCU_ADDR[21..16] (p 7,9)
CTRLMCU_SPI_SCK (p 11)
CTRLMCU_SPI_MOSI (p 11)
CTRLMCU_SPI_#CS (p 11)
CTRLMCU_I2C_SDA (p 11,17,18,20)
CTRLMCU_I2C_SCL (p 11,17,18,20)
FPGA_CFG_DONE (p 10)
CTRLMCU_CLK (p 10)
CTRLMCU_DEBUG_#RESET (p 11)
CTRLMCU_FSMC_#W AIT (p 9)
EEPROM_W P (p 11,15,17,18)
TEST_#RESET (p 10)
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C BRD3200C
Tuesday, January 19, 2010
12 21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Control MCU - Board Control interface
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C BRD3200C
Tuesday, January 19, 2010
12 21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Control MCU - Board Control interface
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C BRD3200C
Tuesday, January 19, 2010
12 21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Control MCU - Board Control interface
R331
0R R331
0R
R344
0R R344
0R
R288
4K7 R288
4K7
R241
470R R241
470R
U18A
24AA024
U18A
24AA024
SDA
5
SCL
6
WP
7
A0
1
A1
2
A2
3
R98
1R R98
1R
C91
100N C91
100N
C100
100N
C100
100N
R91
470R R91
470R
C103
100N
C103
100N
R289
0R R289
0R
LED124
BLUE LED124
BLUE
2
1
L10
BLM21B102S
L10
BLM21B102S
1 2
R94
10K R94
10K
C95
10U C95
10U
LED123
YELLOW LED123
YELLOW
2
1
R93
1K R93
1K
C99
100N
C99
100N
U19B
M25PX16
U19B
M25PX16
VCC
8
VSS
4
C263
100N
C263
100N
U18B
24AA024
U18B
24AA024
VCC
8
VSS
4
U19A
M25PX16
U19A
M25PX16
D
5
C
6
HOLD
7
Q
2
W
3
S
1
C92
10N C92
10N
C97
10N C97
10N
R92
1K R92
1K
R266
0R R266
0R
C98
100N
C98
100N
C96
10N
C96
10N
C102
100N
C102
100N
R341
0R
NM
R341
0R
NM
C101
100N
C101
100N
C105
10U
C105
10U
C90
10N C90
10N
ST9 ST9
1
3
2
4
LED89
RED LED89
RED
2
1
U17C
Control MCU
U17C
Control MCU
NRST
E1
BOOT0
D5
OSC_IN
C1
OSC_OUT
D1
VBAT
B2
VREF-
H1
VREF+
J1
VSSA
G1
VDDA
K1
VDD_1
F7
VDD_2
F6
VDD_3
F5
VDD_4
F4
VDD_5
D2
VSS_1
E7
VSS_2
E6
VSS_3
E5
VSS_4
E4
VSS_5
C2
NC
F8
R99
10K R99
10K
R95
100K R95
100K R96
100K R96
100K
SW 8 SW 8
1
2
3
4
R203
470R R203
470R
R290 0R
NM
R290 0R
NM
TP50 TP50
U17B
Control MCU
U17B
Control MCU
PD0 / OSC_IN / FSMC_D2 [CANRX]
D8
PD1 / OSC_OUT / FSMC_D3 [CANTX]
E8
PD2 / TIM3_ETR / UART5_RX / SDIO_CMD
B7
PD3 / FSMC_CLK [USART2_CTS]
C7
PD4 / FSMC_NOE [USART2_RTS]
D7
PD5 / FSMC_NWE [USART2_TX]
B6
PD6 / FSMC_NWAIT [USART2_RX]
C6
PD7 / FSMC_NE1 / FSMC_NCE2 [USART2_CK]
D6
PD8 / FSMC_D13 [USART3_TX]
K9
PD9 / FSMC_D14 [USART3_RX]
J9
PD10 / FSMC_D15 [USART3_CK]
H9
PD11 / FSMC_A16 [USART3_CTS]
G9
PD12 / FSMC_A17 [USART3_RTS / TIM4_CH1]
K10
PD13 / FSMC_A18 [TIM4_CH2]
J10
PD14 / FSMC_D0 [TIM4_CH3]
H10
PD15 / FSMC_D1 [TIM4_CH4]
G10
PE0 / TIM4_ETR / FSMC_NBL0
D4
PE1 / FSMC_NBL1
C4
PE2 / TRACECK / FSMC_A23
A3
PE3 / TRACED0 / FSMC_A19
B3
PE4 / TRACED1 / FSMC_A20
C3
PE5 / TRACED2 / FSMC_A21
D3
PE6 / TRACED3 / FSMC_A22
E3
PE7 / FSMC_D4 [TIM1_ETR]
H5
PE8 / FSMC_D5 [TIM1_CH1N]
J5
PE9 / FSMC_D6 [TIM1_CH1]
K5
PE10 / FSMC_D7 [TIM1_CH2N]
G6
PE11 / FSMC_D8 [TIM1_CH2]
H6
PE12 / FSMC_D9 [TIM1_CH3N]
J6
PE13 / FSMC_D10 [TIM1_CH3]
K6
PE14 / FSMC_D11 [TIM1_CH4]
G7
PE15 / FSMC_D12 [TIM1_BKIN]
H7
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