5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
UIF_JOYSTICK4
UIF_JOYSTICK3
UIF_JOYSTICK2
UIF_JOYSTICK1
UIF_PB0
UIF_PB1
UIF_PB2
UIF_PB3
BC_BUS_FPGA0
BC_BUS_FPGA1
BC_BUS_FPGA2
BC_BUS_FPGA3
BC_BUS_FPGA4
BC_BUS_FPGA5
BC_BUS_FPGA6
BC_BUS_FPGA7
BC_BUS_FPGA8
BC_BUS_FPGA9
BC_BUS_FPGA10
BC_BUS_FPGA11
BC_BUS_FPGA12
BC_BUS_FPGA13
BC_BUS_FPGA14
BC_BUS_FPGA15
BC_BUS_FPGA16
BC_BUS_FPGA17
BC_BUS_FPGA18
BC_BUS_FPGA19
BC_BUS_FPGA20
BC_BUS_FPGA21
BC_BUS_FPGA22
BC_BUS_FPGA23
BC_BUS_FPGA24
BC_BUS_FPGA25
BC_BUS_FPGA26
BC_BUS_FPGA27
BC_BUS_FPGA_#OE2
BC_BUS_FPGA_#OE3
BC_BUS_FPGA_DIR0
BC_BUS_FPGA_DIR2
BC_BUS_FPGA_DIR3
BC_BUS_FPGA_#OE0
BC_BUS_FPGA_#OE0
BOARD_REVISION[2:0]
PCB_REVISION[2:0]
BC_BUS_CONNECT_SPI
BOARD_REVISION2
BOARD_REVISION1
BOARD_REVISION0
PCB_REVISION2
PCB_REVISION1
PCB_REVISION0
BOARD_REVISION0
BOARD_REVISION1
BOARD_REVISION2
PCB_REVISION0
PCB_REVISION1
PCB_REVISION2
FPGA_ADDR4
FPGA_ADDR5
FPGA_ADDR6
FPGA_ADDR7
FPGA_ADDR8
FPGA_ADDR9
FPGA_ADDR10
FPGA_ADDR11
FPGA_ADDR12
FPGA_ADDR13
FPGA_ADDR14
FPGA_ADDR15
FPGA_ADDR16
FPGA_ADDR17
FPGA_ADDR18
FPGA_ADDR19
FPGA_ADDR20
FPGA_ADDR21
UIF_JOYSTICK0
FPGA_DATA12
FPGA_DATA13
FPGA_DATA14
FPGA_DATA15
FPGA_DATA9
FPGA_DATA10
FPGA_DATA11
BC_BUS_FPGA_#OE1
BC_BUS_FPGA_DIR1
DISPLAY_DATA6
DISPLAY_DATA5
FPGA_DATA0
FPGA_DATA1
FPGA_DATA2
FPGA_DATA3
FPGA_DATA4
FPGA_DATA5
FPGA_DATA6
FPGA_DATA8
FPGA_ADDR0
FPGA_ADDR1
FPGA_ADDR2
FPGA_ADDR3
FPGA_DATA7
DISPLAY_DATA7
DISPLAY_DATA8
FPGA_ADDR23
FPGA_ADDR22
GND
GND
GND
GND
GND
FPGA_VCCO0
FPGA_VCCO0
FPGA_VCCO3
FPGA_VCCO0
FPGA_ADDR[23..0]
(p 6)
BC_BUS_FPGA_#OE[3..0]
(p 14)
BC_BUS_FPGA_DIR[3..0]
(p 14)
FPGA_DATA[15..0]
(p 6)
UIF_JOYSTICK[4..0]
(p 4)
UIF_PB[3..0]
(p 4)
BC_BUS_FPGA[27..0]
(p 14)
AEM_PB
(p 4)
DISPLAY_DATA[17..1]
(p 5,7,9)
BC_BUS_CONNECT_SPI
(p 14)
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
8
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - Memory & BC bus
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
8
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - Memory & BC bus
Size
Designed:
Revision
Sheet
of
Approved:
Sheet Created Date
Sheet Modified Date
Document number
Schematic Title
Design Created Date:
BOM Doc No:
Page Title
C
BRD3200C
Tuesday, January 19, 2010
8
21
A3
JNO
JNO
EFM32 Development Kit - Mainboard
<Cage Code>
Saturday, March 21, 2009
W ednesday, December 03, 2008
TOP
<Schematic Path>
Board Control - Memory & BC bus
TP39
TP39
R58
100K
NM
R58
100K
NM
R60
100K
NM
R60
100K
NM
R65
100K
R65
100K
TP34
TP34
TP38
TP38
TP37
TP37
R63
100K
R63
100K
TP43
TP43
TP41
TP41
U6A
XC3S200A_4_FT256C_SWAP0
U6A
XC3S200A_4_FT256C_SWAP0
IO_L01N_0
C13
IO_L01P_0
D13
IO_L02N_0
B14
IO_L02P_0/VREF_0
B15
IO_L03N_0
D11
IO_L03P_0
C12
IO_L04N_0
A13
IO_L05N_0
A12
IO_L05P_0
B12
IO_L06N_0/VREF_0
E10
IO_L10N_0/GCLK7
A9
IO_L10P_0/GCLK6
C9
IO_L11N_0/GCLK9
D8
IO_L11P_0/GCLK8
C8
IO_L12N_0/GCLK11
B8
IO_L12P_0/GCLK10
A8
IO_L13N_0
C7
IO_L14N_0/VREF_0
E7
IO_L14P_0
F8
IO_L15N_0
B6
IO_L15P_0
A6
IO_L16N_0
C6
IO_L16P_0
D7
IO_L17N_0
C5
IO_L17P_0
A5
IO_L18N_0
B4
IO_L18P_0
A4
IO_L19N_0
B3
IO_L19P_0
A3
IO_L20N_0/PUDC_B
D5
IO_L20P_0/VREF_0
C4
IP0_0
D6
IP4_0
F9
IP5_0
F10
IP1_0
D12
IP3_0
F7
IP2_0
E6
IP6_0/VREF_0
E9
VCCO_0
B5
VCCO_0
E8
VCCO_0
B9
VCCO_0
B13
IO_L04P_0
A14
IO_L08P_0
B10
IO_L08N_0
A10
IO_L07P_0
C11
IO_L07N_0
A11
IO_L09N_0/GCLK5
D9
IO_L13P_0
A7
IO_L06P_0
D10
IO_L09P_0/GCLK4
C10
TP42
TP42
TP40
TP40
TP36
TP36
U6D
XC3S200A_4_FT256C_SWAP0
U6D
XC3S200A_4_FT256C_SWAP0
IO_L01N_3
C1
IO_L01P_3
C2
IO_L02N_3
D3
IO_L02P_3
D4
IO_L03N_3
E1
IO_L03P_3
D1
IO_L05N_3
E2
IO_L05P_3
E3
IO_L09P_3
G3
IO_L10N_3
H5
IO_L10P_3
H6
IO_L11N_3/LHCLK1
H1
IO_L11P_3/LHCLK0
G2
IO_L12N_3/IRDY2/LHCLK3
J3
IO_L12P_3/LHCLK2
H3
IO_L14N_3/LHCLK5
J1
IO_L14P_3/LHCLK4
J2
IO_L15N_3/LHCLK7
K1
IO_L15P_3/TRDY2/LHCLK6
K3
IO_L16N_3
L2
IO_L16P_3/VREF_3
L1
IO_L17N_3
J6
IO_L17P_3
J4
IO_L18N_3
L3
IO_L18P_3
K4
IO_L19N_3
L4
IO_L19P_3
M3
IO_L20N_3
N1
IO_L20P_3
M1
IO_L22N_3
P1
IO_L22P_3
N2
IO_L23N_3
P2
IO_L23P_3
R1
IO_L24N_3
M4
IO_L24P_3
N3
IP_L04N_3/VREF_3
F4
IP_L04P_3
E4
IP_L06N_3/VREF_3
G5
IP_L06P_3
G6
IP_L13N_3
J7
IP_L13P_3
H7
IP_L21N_3
K6
IP_L21P_3
K5
IP_L25N_3/VREF_3
L6
IP_L25P_3
L5
IO_L09N_3
H4
IO_L08P_3
F1
IO_L08N_3/VREF_3
G1
IO_L07P_3
F3
IO_L07N_3
G4
VCCO_3
D2
VCCO_3
H2
VCCO_3
M2
VCCO_3
J5
TP44
TP44
TP45
TP45
R59
100K
NM
R59
100K
NM
TP35
TP35
R64
100K
R64
100K
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