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EDM01-33v1 DAG_7.5G4_Card_User_Guide

©2008 Endace Technology Ltd. Confidential - Version 1 - November 2008

45

Dagclock Statistics reset

Statistics are reset to zero when the following occur:

•

Loading a DAG driver

•

Loading firmware

•

dagclock

with a

-x

option

•

dagclock

with a

set or

reset

command.

Example

To view the default

dagclock

configuration:

dagclock –d0

The following is the output from DAG card that has its clock reference connected. The clock

statistics have been reset since the card was last synchronized.

Note:

Values will differ for

each DAG card type.

muxin rs422
muxout none
status Synchronised Threshold 596ns Failures 0 Resyncs 0
error Freq -30ppb Phase -60ns Worst Freq 75ppb Worst Phase 104ns
crystal Actual 100000028Hz Synthesized 67108864Hz
input Total 3765 Bad 0 Singles Missed 5 Longest Sequence Missed 1
start Thu Apr 28 13:32:45 2007
host Thu Apr 28 14:35:35 2007
dag Thu Apr 28 14:35:35 2007

Note:

For a description of the

dagclock

output see

Dagclock output explained

(page ).

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Summary of Contents for DAG 5.2X

Page 1: ...DAG 7 5G4 Card User Guide EDM01 33...

Page 2: ...Disclaimer Whilst every effort has been made to ensure accuracy neither Endace Technology Limited nor any employee of the company shall be liable on any ground whatsoever to any party in respect of de...

Page 3: ...jumper settings 11 Boot LEDs 11 Pluggable Optical Transceivers 12 Overview 12 Optical modules 12 Power Input 13 Splitter Losses 13 Pluggable Copper Transceivers 13 Configuring the DAG card 15 Introduc...

Page 4: ...twork Time Protocol 42 Timestamps 43 Example 43 Dagclock 44 Dagclock Statistics reset 45 Dagclock output explained 46 Card with Reference 48 Overview 48 Pulse Signal from External Source 48 Connecting...

Page 5: ...G 7 5G4 card provides independent four port Ethernet network monitoring at Gigabit speeds and supports header only or variable length capture It is capable of transmitting and receiving on each channe...

Page 6: ...erver User Guide EDM11 01 ERF types PN01 13 DAG Card Quick Start Guide This User Guide and the EDM04 01 DAG Software Installation Guide are also available in PDF format on the installation CD shipped...

Page 7: ...te for IP packets from 48 to 9600 bytes Conditioned clock with PPS input and local synchronization capability PCIe x4 Gen 1 0a 8 Gigabits per second Raw Actual performance of PCIe will depend on the m...

Page 8: ...CK provides high resolution per packet timestamps which can be accurately synchronized Note For further information on the DUCK and time synchronization see Synchronizing Clock Time 41 page later in t...

Page 9: ...sted below to apply to your network please contact your Network Administrator for further information Supported Line Types The line characteristics supported by the DAG 7 5G4 card are described below...

Page 10: ...the filter and load balancing outputs It also receives the physical port the packet arrived on and calculates a classification also known as color for the packet Colorizer and Drop Block The color is...

Page 11: ...Release TERF TR TERF The Timed Release TERF TR TERF module is a option that enables you to transmit an ERF stream while reproducing the timestamps of the packets within that stream It is able to trans...

Page 12: ......

Page 13: ...d to partially or completely fail 1 Turn power to the computer OFF 2 Remove the PCIe bus slot screw and cover 3 Using an approved ESD protection device attach the end with the strap to your wrist and...

Page 14: ...nsists of an optical fiber or copper transmitter and receiver Note The DAG 7 5G4 supports both optical and copper transceivers The DAG 7 5G4G4 has an 8 pin RJ45 socket located below the optical port c...

Page 15: ...e 2 3 or jumper not fitted Normal operation of the DAG card FF jumper settings Jumper set between Definition 1 2 Loads the factory image into the FPGA at power on 2 3 or jumper not fitted Loads the us...

Page 16: ...ular SFP module that is fitted to the DAG 4 5Z2 4 5Z8 card Optics modules are supplied in either Single or Multi mode See the following table for details Optical power is measured in dBm This is decib...

Page 17: ...ither marked on their packaging or described in their accompanying documentation General guidelines are A 50 50 splitter will have an insertion loss of between 3 dB and 4 dB on each output 90 10 split...

Page 18: ......

Page 19: ...guring the DAG card Before configuring the FPGA you should ensure that dagmem has been run and memory allocated to each installed DAG card dagload has been run so that all DAG drivers have been instal...

Page 20: ...iginally shipped from the factory By default the DAG 7 5G4 card boots user image 1 unless the Force factory jumper is fitted For more details on the Force factory jumper see Boot jumper settings 11 pa...

Page 21: ...e computer and in the DAG card Newer versions are automatically loaded onto the DAG card and programmed into the FPGA See Endace recommends you use the dagrom r command when loading images from the co...

Page 22: ...SWID key with the one supplied l hold bus Hold PBI bus from XScale DAG 3 7T only m swid key key Hexadecimal key for writing the Software ID aka SWID o swid rom read Read SWID from ROM p program curren...

Page 23: ...0 19 01 active user 2 user 3 Card Serial 3006575 Preparing the DAG card for use Before configuring the DAG 7 5G4 card you must run the following dagconfig command to set the default parameters in the...

Page 24: ...ou should run the dagconfig tool without arguments to display the current card configuration and verify the firmware has been loaded correctly To display the default configuration for the first card u...

Page 25: ...packets to be all generated as multiples of 8 bytes 64 bit aligned align64 before being received by the host Not a configurable option auto_neg noauto_neg Note From DAG software 3 1 0 onwards nic non...

Page 26: ...lt drop nodrop Determines if the DAG card s memory holes are de coupled In drop mode the memory holes are de coupled If the data rate on one memory hole slows the data rate on any other memory holes i...

Page 27: ...ayed as a ratio as shown below mem X Y where X is the memory allocated in MB to the rx stream Y is the memory allocated in MB to the tx stream If there are multiple rx or tx streams memory can be allo...

Page 28: ...t framers set auto mode Example dagconfig d0 reset rx and tx Streams Indicates the number of rx and tx streams are available on the DAG card Not configurable Stream information relates to the setting...

Page 29: ...e Therefore a slen of 48 will produce a 64 byte capture record made up of 48 bytes plus the number of bytes in the ERF header steer The algorithm to use to steer the incoming packet Option Description...

Page 30: ...in this mode the timing for each port is independent This is shown in the following example where Packet A and Packet B are transmitted at the same time even though their timestamps are one second ap...

Page 31: ...he slen value will be captured at its actual size therefore producing a shorter record which saves bandwidth and storage space Example The example below shows a configuration for variable length full...

Page 32: ...e in conjunction with the porta or portb options to get individual only multi port cards h help Displays the MAN pages The information displayed is dynamically based on the DAG card and does not work...

Page 33: ...is present on the link 0 indicates the condition is not present on the link Ethernet Port pll_lock lock los reset_done link lof A 1 1 0 0 1 0 B 1 1 0 0 1 0 C 1 1 0 0 1 0 D 1 1 0 0 1 0 A definition of...

Page 34: ...8 Universal counters The counters contain details of the number of frames and any errors The counters are latch and clear so values indicate the amount of data since the last time the counters were re...

Page 35: ...which can then be viewed using dagbits or converted to other formats using dagconvert When capturing high speed data Endace recommends you use dagsnap see Capturing data at high speed 33 page For furt...

Page 36: ...iting data to disk in chunks This option may not be available on all operating systems m NUM Write at most NUM megabytes of data per call to the DAG API default is 4 MiB o FILE fname FILE Write the ca...

Page 37: ...net reached 0xNNNNNNNN The same message is also printed to log var log messages file In addition when the computer buffer fills the Data Capture LED on the card will flash or flicker or may go OFF com...

Page 38: ...CRCs PoS and Ethernet a Set legacy format to ATM this is the default b Treat ERF timestamps as big endian c Print real time progress reports as dagbits captures traffic This is a useful indicator tha...

Page 39: ...ly makes sense when capturing packets from a DAG card i e when used in conjunction with the d flag t NUM Terminate dagbits if any ERF record type does not match NUM U NUM Process at most NUM records i...

Page 40: ...cap o outfile pcap To convert a file from ERF format to pcap format dagconvert T erf pcap i infile erf o outfile pcap To convert a file from pcap format to ERF format ensuring the ERF records are 64 b...

Page 41: ...cludes 0 dag1 and dev dag3 to refer to DAG cards and 0 2 dag1 1 and dev dag2 0 to refer to specific streams on cards f FILTERS A comma delimited list of filters to be applied to the data Supported fil...

Page 42: ...ng dsm_loader d0 f filter_filename If you have configured DSM filtering but want to revert to normal capture mode you will need to bypass DSM filtering to the original null configuration using dsm_loa...

Page 43: ...ace com support If packets have been captured without using the align64 option you can convert the trace files so that they can be transmitted by using In addition the length of the ERF records to be...

Page 44: ...d for any reason To allow for this TR TERF can be optionally configured not to retransmit any packets marked with the rxerror receive error flag Usage Notes The following points should be noted when u...

Page 45: ...etween sets of DAG cards or between DAG cards and coordinated universal time UTC You can obtain an accurate time reference by connecting an external clock to the DAG card using the time synchronizatio...

Page 46: ...the computer clock directly In both cases the computer clock time is loaded onto the DAG clock when the DAG card is started dagload dagreset dagrom p When clock synchronization is enabled the DAG card...

Page 47: ...that are not active being set to zero In this way the interpretation of the timestamp does not need to change when higher resolution clock hardware is available The DAG 7 5G4 implements the 27 most si...

Page 48: ...exiting K NUM Set the synchronization timeout in seconds default is 60 seconds l NUM Set the Health threshold in nanoseconds default is 596ns v Increase output verbosity V Display version information...

Page 49: ...at has its clock reference connected The clock statistics have been reset since the card was last synchronized Note Values will differ for each DAG card type muxin rs422 muxout none status Synchronise...

Page 50: ...s value can be adjusted using the dagclock l option Failures This is a count of the number of times the DAG card has become Not Synchronized Resyncs This is a count of the number of times the DAG card...

Page 51: ...ime pulses are considered Bad if they were not received 1 second approximately after the last time pulse These may be caused by noise Singles missed The number of times a single time pulse failed to b...

Page 52: ...ernal source as follows dagclock d0 Output muxin rs422 muxout none status Synchronised Threshold 596ns Failures 0 Resyncs 0 error Freq 30ppb Phase 15ns Worst Freq 238ppb Worst Phase 326ns crystal Actu...

Page 53: ...ieved with this method is not as accurate as using an external reference source such as GPS The DUCK clock is synchronized to a computer clock by setting input synchronization selector to overflow as...

Page 54: ...the host and also act as a master for the second DAG card Synchronizing with Each Other Although the master DAG card s clock drifts against UTC the DAG cards will be locked together This is achieved b...

Page 55: ...the computer clock and output a RS 422 synchronization signal to the second DAG card as follows dagclock d0 none overin overout Output muxin over muxout over status Synchronised Threshold 11921ns Fail...

Page 56: ...AL Normally you connect the GPS input to the PPS A channel input pins 3 and 6 The DAG card can also output a synchronization pulse for use when synchronizing two DAG cards i e without a GPS input The...

Page 57: ...ts the following ERF Types ERF Type Description 2 TYPE_ETH Ethernet Variable Length Record 16 TYPE_DSM_COLOR_ETH Ethernet Variable Length Record The ERF file contains a series of ERF records with each...

Page 58: ...ets are snapped off at snap length and shorter packets are padded up to the snap length rlen resembles snap length Setting novarlen and slen greater than 256 bytes is wasteful of bandwidth 3 Truncated...

Page 59: ...MC_RAW_ CHANNEL Multi channel Raw link data 9 TYPE_MC_AAL5 Multi channel AAL5 frame 10 TYPE_COLOR_HDLC_ POS HDLC format like TYPE_HDLC_POS but with the LCNTR field reassigned as COLOR 11 TYPE_COLOR_ET...

Page 60: ..._ETH record format Field Description Offset 1 byte Number of bytes not captured from start of frame Typically used to skip link layer headers when not required in order to save bandwidth and space Not...

Page 61: ...r1 and so on 14 hlb0 CRC calculation output bit 15 hlb1 parity calculation output bit Offset 1 byte Number of bytes not captured from the start of the frame This is typically used to skip link layer h...

Page 62: ...ts in automatic support across ERF types Bit 7 of the ERF type field is used to indicate that Extension Header s are present If set to 1 Extension Headers are present The Extension Header type field i...

Page 63: ...ckage in use Any compiler errors or warnings when building DAG driver or tools For Linux and FreeBSD messages generated when DAG device driver is loaded These can be collected from command dmesg or fr...

Page 64: ......

Page 65: ...shown below Version Date Reason 1 November 2008 First release Based on 7 5G2 Status Description Preliminary The products described in this technical document are in development and have yet to comple...

Page 66: ......

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