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Endace Measurement Systems.

http://www.endace.com

EDM01.05-10r1 DAG 4.3S Card User Manual

Revision 6. 22 September 2005.

1.3 DAG 4.3S Card Architecture

, continued

Figure

Figure 1-2 shows the DAG 4.3S card major components and data flow.

Optics Module

Framer

Coprocessor

Connector

DAG 4.3

FPGA

CPLD

Time Stamping

Clock

Flash

ROM

Sync

In/Out

FIFO

LED’s

PCI-X 64-Bit 66-133MHz

Figure 1-2. DAG 4.3S Card Major Components and Data Flow.

1.4 DAG Card Extended Functions

Description

The DAG 4.3S functionality can be extended in many ways.

The co-processor allows for advanced features such as IP packet filtering
in hardware at line rate. Contact the Endace customer support team at

[email protected]

to enable effective use of extended functions.

Summary of Contents for DAG 4.3S

Page 1: ...EDM01 05 10 DAG 4 3S Card User Manual 2 5 5r1...

Page 2: ...46 Hamilton 2001 New Zealand Phone 64 7 839 0540 Fax 64 7 839 0543 support endace com www endace com Endace USA Ltd Suite 220 11495 Sunset Hill Road Reston Virginia 20190 United States of America Phon...

Page 3: ...mmission FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and...

Page 4: ...Power Input 9 3 2 Splitter Losses 10 4 0 CONFIDENCE TESTING 11 4 1 Interpreting DAG 4 3S Card LED Status 11 4 2 DAG 4 3S Card Capture Session 13 4 3 Configuration in WYSYCC Style 15 4 4 DAG 4 3S Card...

Page 6: ...tem Requirements 1 1 User Manual Purpose Description The purpose of this DAG 4 3S Card User Manual is to describe DAG 4 3S Card Product Description DAG 4 3S Card Architecture DAG Card Extended Functio...

Page 7: ...ording of all header information payload and with a high precision timestamp subject to bus and processor availability The DAG 4 3S is capable of transmitting packets at 100 line rate while simultaneo...

Page 8: ...r Connector DAG 4 3 FPGA CPLD Time Stamping Clock Flash ROM Sync In Out FIFO LED s PCI X 64 Bit 66 133MHz Figure 1 2 DAG 4 3S Card Major Components and Data Flow 1 4 DAG Card Extended Functions Descri...

Page 9: ...S Card Ferrite Component 1 6 DAG 4 3S Card System Requirements Description The DAG 4 3S card and associated data capture system minimum operating requirements are PC at least Intel Xeon 1 8GHz or fast...

Page 10: ...05 10r1 DAG 4 3S Card User Manual 5 Revision 6 22 September 2005 1 6 DAG 4 3S Card System Requirements continued Different system For advice on using a system substantially different from that specifi...

Page 11: ...following topics of information Installation of Operating System and Endace Software Insert DAG 4 3S Card into PC DAG 4 3S Card Port Connector 2 1 Installation of Operating System and Endace Software...

Page 12: ...synchronization This socket should never be connected to an Ethernet network or telephone line 2 4 Pluggable Optical Transceivers Description Some newer versions of the DAG 4 3S cards are available w...

Page 13: ...com EDM01 05 10r1 DAG 4 3S Card User Manual 8 Revision 6 22 September 2005 2 4 Pluggable Optical Transceivers continued Description continued Figure Figure 2 1 shows the pluggable optical transceiver...

Page 14: ...art No Fibre Data Rate Min Max Pwr dBm in Min Max Pwr dBm out Min Max Wavelength in Min Max Wavelength out Finisar FTRJ1321S SMF 2488 18 0 9 5 3 1270 1600 1260 1360 Agilent HFCT5942 SMF 2488 19 3 10 3...

Page 15: ...Losses Description Splitters have the insertion losses marked on packaging or in accompanying documentation A 50 50 splitter will have an insertion loss of between 3 dBm and 4 dBm on each output 90 1...

Page 16: ...g this process In this chapter This chapter covers the following sections of information Interpreting DAG 4 3S Card LED Status DAG 4 3S Card Capture Session Configuration in WYSYCC Style DAG 4 3S Card...

Page 17: ...tect Illuminates when light is detected LED 6 LOF Loss of frame Illuminates the framer loses lock on a valid SONET SDH stream LED 7 PPS Out Pulse Per Second Out flashes indicate card is sending a cloc...

Page 18: ...rts light levels are correct using an optical power meter The card receiver ports are the lower half of the LC style connector the closest to the LEDs Cover unused card transmit ports with LC style pl...

Page 19: ...s the dagfour tool is supplied Calling dagfour without arguments lists current settings The dagfour h prints a help listing on tool usage Step 6 Configure DAG for Normal Use The dagfour default comman...

Page 20: ...nges dag endace dagfour d dag0 atm light laser link noreset OC48c nofcl noeql sonet master scramble ATM discard pscramble rxpkts txpkts packetA drop 0 pcix 133MHz 64 bit nodrop routesource stream0 buf...

Page 21: ...with 64 bit alignment default 32 bit Inspect interface statistics Once the card has been configured as expected the interface statistics should be inspected to see if the card is locked to the data st...

Page 22: ...nto the SONET SDH stream check connections and optical signal level PathBIP SONET SDH Path Bit Interleaved Parity error The link is impaired check connections and optical signal level PathREI SONET SD...

Page 23: ...ince last reading When in ATM mode HEC_Fail Number of ATM Header Error Checksum Failures since last reading PoS OC 48 stream example An example for a card locked to a PoS OC 48c stream carrying a cons...

Page 24: ...hBIP PathREI LCD RxCells RxIdles HEC_Fail PathLabel 0 0 0 0 0 0 6013310 219055106 0 0x13 0 0 0 0 0 0 151186 5507454 0 0x13 0 0 0 0 0 0 152489 5554933 0 0x13 0 0 0 0 0 0 152489 5554941 0 0x13 POS confi...

Page 25: ...ONET PoS links it can happen that there is very little or no data information received This typically indicates incorrect scrambling settings While a default is provided that matches typical link sett...

Page 26: ...C type and configuration 3 Host PC operating system version 4 DAG software version package in use 5 UNIX operating system only Any compiler errors or warnings when building DAG driver or tools 6 UNIX...

Page 27: ...Endace Measurement Systems http www endace com EDM01 05 10r1 DAG 4 3S Card User Manual 22 Revision 6 22 September 2005 USE THIS SPACE FOR NOTES...

Page 28: ...ory For a typical measurement session ensure the driver is loaded the firmware has been downloaded and the card is configured The integrity of the card s physical layer is then set and checked Procedu...

Page 29: ...unded down to the nearest multiple of 4 Packets longer than slen are truncated Packets shorter than slen will produce shorter records saving bandwidth and storage space Full packet capture for example...

Page 30: ...a signal killall dagsnap or key strokes CTL C Dagsnap can also be configured to run for a fixed number of seconds and then exit using the s option 5 2 High Load Performance Description As the DAG car...

Page 31: ...isk array If records are being processed in real time a faster host CPU may be required Increasing buffer size The host PC buffer can be increased to deal with bursts of high traffic load on the netwo...

Page 32: ...cket transmission The DAG will not respond to ARP ping or router discovery protocols It will only transmit packets explicitly provided by the user This capability allows the DAG card to be used as a s...

Page 33: ...ion with dagflood the file can be tested with dagbits dagbits vvc align64 f tracefile erf If a captured trace file is not available the daggen program is capable of generating trace files containing s...

Page 34: ...amount of memory allocated to receive stream 0 in MB and Y is the amount of memory allocated to transmit stream 1 in MB By default the memory is evenly split between the receive streams the transmit s...

Page 35: ...ormance may be limited by the host PC CPU and memory performance The dagfwddemo program The dagfwddemo program is provided as a demonstration of how this can be achieved This program forwards packets...

Page 36: ...avoid time variance between sets of DAG cards or between DAG cards and coordinated universal time UTC Accurate time reference can be obtained from an external clock by connecting to the DAG card using...

Page 37: ...al input synchronize to host clock auxin Aux input unused rs422out Output the rs422 input signal loop Output the selected input hostout Output from host unused overout Internal output master card set...

Page 38: ...endace dagclock d dag0 none overin muxin overin muxout NOTE dagclock should be run only after appropriate Xilinx images have been loaded If the Xilinx images must be reloaded the dagclock command must...

Page 39: ...turn utilises NTP This provides a master signal to the second card In this case connect synchronization connectors with a standard RJ 45 Ethernet cross over cable Configure one card to synchronize to...

Page 40: ...connect DAG and or the TDS 2 module to active Ethernet or telephone equipment Testing signal For Linux and FreeBSD when a synchronization source is connected the driver outputs some messages to the co...

Page 41: ...uld be connected to the A channel input pins 3 and 6 The DAG can also output a synchronization pulse used when synchronizing two DAGs without a GPS input Synchronization output is generated on the Out...

Page 42: ...le endian Pentium native byte order All other fields are in big endian network byte order All payload data is captured as a byte stream no byte re ordering is applied Table Table 7 1 shows the Type 1...

Page 43: ...6 TYPE_MC_RAW Multi channel Raw link data 7 TYPE_MC_ATM Multi channel ATM Cell 8 TYPE_MC_RAW_CHANNEL Multi channel Raw Link Data 9 TYPE_MC_AAL5 Multi channel AAL5 frame 10 TYPE_COLOR_HDLC_POS HDLC POS...

Page 44: ...bit fixed point number representing seconds since midnight on the first of January 1970 The high 32 bits contain the integer number of seconds while the lower 32 bits contain the binary fraction of th...

Page 45: ...Example code Here is some example code showing how a 64 bit ERF timestamp erfts can be converted into UNIX struct timeval representation tv unsigned long long lts struct timeval tv lts erfts tv tv_sec...

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