Emerson ATCA-F120, Installation And Use Manual

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Functional Description
ATCA-F120 Installation and Use (6806800D06F)
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The main features of the CPU are as follows:
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On-die L1 cache
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On-die L2 cache
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DDR2 memory controller and interface
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Local bus controller and interface
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DUART
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Programmable interrupt controller
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Two 32-bit/66 MHz PCI buses
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x1 PCI Express interface to RTM
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4-channel DMA controller
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Four 10/100/1000 GBit Ethernet MACs
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Two I2C controller
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Security engine
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XOR engine
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JTAG interface
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Watchdog (not used on ATCA-F120)
4.4 Main Memory
The memory controller resides inside the MPC8548E PowerQUICC III CPU. The memory bus is
64 bit wide and ECC protected. It connects the CPU to the on-board memory modules. The
memory data bus runs at a maximum frequency of 266 MHz providing a total bandwidth of
4.267 GBytes/s.
The ATCA-F120 supports up to 1 GByte of main memory.
4.5 Glue Logic FPGA
The ATCA-F120 provides a Glue Logic FPGA which is used for various purposes. Details are given
in the following two subsections.