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Elmicro S12compact User Manual Download Page 42

The following assembly listing is part of the monitor program.

It shows the original vector addresses (1st column from the left) as

well as the redirected addresses in RAM (2nd column):

FF80 : 3F43               dc.w  TP_RAMTOP-189

; reserved

FF82 : 3F46               dc.w  TP_RAMTOP-186

; reserved

FF84 : 3F49               dc.w  TP_RAMTOP-183

; reserved

FF86 : 3F4C               dc.w  TP_RAMTOP-180

; reserved

FF88 : 3F4F               dc.w  TP_RAMTOP-177

; reserved

FF8A : 3F52               dc.w  TP_RAMTOP-174

; reserved

FF8C : 3F55               dc.w  TP_RAMTOP-171

; PWM Emergency Shutdown

FF8E : 3F58               dc.w  TP_RAMTOP-168

; Port P

FF90 : 3F5B               dc.w  TP_RAMTOP-165

; CAN4 transmit

FF92 : 3F5E               dc.w  TP_RAMTOP-162

; CAN4 receive

FF94 : 3F61               dc.w  TP_RAMTOP-159

; CAN4 errors

FF96 : 3F64               dc.w  TP_RAMTOP-156

; CAN4 wake-up

FF98 : 3F67               dc.w  TP_RAMTOP-153

; CAN3 transmit

FF9A : 3F6A               dc.w  TP_RAMTOP-150

; CAN3 receive

FF9C : 3F6D               dc.w  TP_RAMTOP-147

; CAN3 errors

FF9E : 3F70               dc.w  TP_RAMTOP-144

; CAN3 wake-up

FFA0 : 3F73               dc.w  TP_RAMTOP-141

; CAN2 transmit

FFA2 : 3F76               dc.w  TP_RAMTOP-138

; CAN2 receive

FFA4 : 3F79               dc.w  TP_RAMTOP-135

; CAN2 errors

FFA6 : 3F7C               dc.w  TP_RAMTOP-132

; CAN2 wake-up

FFA8 : 3F7F               dc.w  TP_RAMTOP-129

; CAN1 transmit

FFAA : 3F82               dc.w  TP_RAMTOP-126

; CAN1 receive

FFAC : 3F85               dc.w  TP_RAMTOP-123

; CAN1 errors

FFAE : 3F88               dc.w  TP_RAMTOP-120

; CAN1 wake-up

FFB0 : 3F8B               dc.w  TP_RAMTOP-117

; CAN0 transmit

FFB2 : 3F8E               dc.w  TP_RAMTOP-114

; CAN0 receive

FFB4 : 3F91               dc.w  TP_RAMTOP-111

; CAN0 errors

FFB6 : 3F94               dc.w  TP_RAMTOP-108

; CAN0 wake-up

FFB8 : 3F97               dc.w  TP_RAMTOP-105

; FLASH

FFBA : 3F9A               dc.w  TP_RAMTOP-102

; EEPROM

FFBC : 3F9D               dc.w  TP_RAMTOP-99

; SPI2

FFBE : 3FA0               dc.w  TP_RAMTOP-96

; SPI1

FFC0 : 3FA3               dc.w  TP_RAMTOP-93

; IIC

FFC2 : 3FA6               dc.w  TP_RAMTOP-90

; BDLC

FFC4 : 3FA9               dc.w  TP_RAMTOP-87

; Self Clock Mode

FFC6 : 3FAC               dc.w  TP_RAMTOP-84

; PLL Lock

FFC8 : 3FAF               dc.w  TP_RAMTOP-81

; Pulse Accu B Overflow

FFCA : 3FB2               dc.w  TP_RAMTOP-78

; MDCU

FFCC : 3FB5               dc.w  TP_RAMTOP-75

; Port H

FFCE : 3FB8               dc.w  TP_RAMTOP-72

; Port J

FFD0 : 3FBB               dc.w  TP_RAMTOP-69

; ATD1

FFD2 : 3FBE               dc.w  TP_RAMTOP-66

; ATD0

FFD4 : 3FC1               dc.w  TP_RAMTOP-63

; SCI1

FFD6 : 3FC4               dc.w  TP_RAMTOP-60

; SCI0

FFD8 : 3FC7               dc.w  TP_RAMTOP-57

; SPI0

FFDA : 3FCA               dc.w  TP_RAMTOP-54

; Pulse Accu A Input Edge

FFDC : 3FCD               dc.w  TP_RAMTOP-51

; Pulse Accu A Overflow

FFDE : 3FD0               dc.w  TP_RAMTOP-48

; Timer Overflow

FFE0 : 3FD3               dc.w  TP_RAMTOP-45

; TC7

FFE2 : 3FD6               dc.w  TP_RAMTOP-42

; TC6

FFE4 : 3FD9               dc.w  TP_RAMTOP-39

; TC5

FFE6 : 3FDC               dc.w  TP_RAMTOP-36

; TC4

FFE8 : 3FDF               dc.w  TP_RAMTOP-33

; TC3

FFEA : 3FE2               dc.w  TP_RAMTOP-30

; TC2

FFEC : 3FE5               dc.w  TP_RAMTOP-27

; TC1

FFEE : 3FE8               dc.w  TP_RAMTOP-24

; TC0

FFF0 : 3FEB               dc.w  TP_RAMTOP-21

; RTI

FFF2 : 3FEE               dc.w  TP_RAMTOP-18

; IRQ

FFF4 : 3FF1               dc.w  TP_RAMTOP-15

; XIRQ

FFF6 : 3FF4               dc.w  TP_RAMTOP-12

; SWI

FFF8 : 3FF7               dc.w  TP_RAMTOP-9 

; Illegal Opcode

FFFA : 3FFA               dc.w  TP_RAMTOP-6 

; COP Fail

FFFC : 3FFD               dc.w  TP_RAMTOP-3 

; Clock Monitor Fail

FFFE : F000               dc.w  main

; Reset

S12compact

40

Summary of Contents for S12compact

Page 1: ...S12compact Hardware Version 1 10 User Manual July 4 2008...

Page 2: ...ial hardware and firmware In no event shall the manufacturer or its supplier be liable for any damages whatsoever including without limitation damages for loss of business profits business interruptio...

Page 3: ...ntegrated A D Converter 15 Operating Modes BDM Support 14 Clock Generation and PLL 13 Reset Generation 12 Controller Core Power Supply 12 Schematic Diagram 12 6 Circuit Description 11 5 Mechanical Dim...

Page 4: ...d EEPROM 38 Autostart Function 38 Serial Communication 38 8 TwinPEEKs Monitor 37 Additional Information on the Web 37 Startup Code 37 Behaviour after Reset 37 7 Application Hints 36 Bus Interface 34 C...

Page 5: ...full 16 bit data paths throughout An integrated PLL circuit allows adjusting perfor mance vs current consumption according to the needs of the user application In addition to the on chip controller fu...

Page 6: ...d serial port for IF Modules RS232 RS485 LIN w Indicator LED w Sound Transducer Buzzer w High Speed phys CAN Interface w Reset Button w up to 70 free General Purpose I Os w eight additional digital in...

Page 7: ...Flash Memory w RS232 Cable Sub D9 w USB Cable only for option USB w set of header connectors two 72 pin male headers w User Manual this document w Schematic Diagrams w CD ROM contains assembler softw...

Page 8: ...0 connector X2 and PC is simply made using the flat ribbon cable which is in the box w On the PC start a Terminal Program An easy to use Terminal Program is OC Console which is available at no charge...

Page 9: ...3 Parts Location Diagram Place Plan Component Side User Manual 7...

Page 10: ...Solder Bridges on the solder side of the PCB S12compact 8...

Page 11: ...no CAN Bus termination on board closed on board CAN Bus termination active BR3 BUZZ open Port pin PT2 freely available closed PT2 controls buzzer BR4 T1IN open Port pin TXD0 PS1 freely available close...

Page 12: ...al supply of VREF required closed IC10 delivers reference voltage VREF for the 16 bit A D Converter IC11 and the 16 Bit D A Converter IC12 BR10 DFLE open Port pin MISO1 PH0 freely available closed MIS...

Page 13: ...reference point 0 0 is located at the south west corner of the PCB The PCB is orientated vertically as shown in the Parts Location Diagram see above All data for holes drills B refer to the center of...

Page 14: ...he three terminal pairs mentioned above must be decoupled carefully A ceramic capacitor of at least 100nF should be connected directly at each pair C15 C16 C17 It is recommended to add a 10 F electrol...

Page 15: ...below the level required for proper MCU operation To prevent collisions with the bidirectional RESET pin of the MCU the LVI circuit IC2 has an open drain output In the inactive state it is pulled up h...

Page 16: ...tray capacitance as possible in respect to XTAL and EXTAL With an OSCCLK of 16MHz the internal bus speed ECLK becomes 8MHz by default To realize higher bus clock rates the PLL has to be engaged The MC...

Page 17: ...ference Divider SYNR S12_SYNR set up Synthesizer Multiplier the following dummy write has no effect except consuming some cycles this is a workaround for erratum MUCTS00174 mask set 0K36N only CRGFLG...

Page 18: ...ally usually controlled by a PC based debugging program The 6 pin header X1A uses the suggested standard BDM12 connector layout Connector X1B carries additional MCU signals which are normally not need...

Page 19: ...12 allows ECLK 6 24MHz 2nd sample time 2 ATD clocks ATD0CTL4 BM_PRS2 BM_PRS0 Func Perform single channel ATD conversion Args channel 0 7 Retn unsigned left justified 10 bit result UINT16 getATD0 UINT8...

Page 20: ...dule is left at it s default position The initialization sequence just takes care for setting up the EEPROM Clock Divider according to the quartz crystal frequen cy The write function wrSectEETS copie...

Page 21: ...rase sector dest src ECMD EETS_CMD_SERASE ESTAT BM_CBEIF if ESTAT BM_PVIOL BM_ACCERR return 4 while ESTAT BM_CBEIF 0 program 1st word dest src ECMD EETS_CMD_PROGRAM ESTAT BM_CBEIF if ESTAT BM_PVIOL BM...

Page 22: ...g C header file File S12CO_LED H V1 00 ifndef __S12CO_LED_H define __S12CO_LED_H Macros define initLED PORTE 0x80 DDRE 0x80 define offLED PORTE 0x80 define onLED PORTE 0x80 define toggleLED PORTE 0x80...

Page 23: ...annel 2 TIOS BM_2 DDRT BM_2 enable Interrupt for channel 2 TIE BM_2 timer disconnected from PT2 pin TCTL2 BM_OM2 BM_OL2 period is in s void setFreqOut UINT16 period UINT16 tticks tticks period S12_ECL...

Page 24: ...ines If the RS232 transceiver IC3 is not needed the dedicated MCU pins can be used freely after opening the four solder bridges BR4 BR7 To connect the S12compact to a PC a 10 wire flat ribbon cable ca...

Page 25: ...5 respectively USB Interface IC15 FT232BM is an USB UART This chip provides a transpa rent conversion from RS232 to USB and back The communication protocol is implemented according to the current USB...

Page 26: ...normally not required The USB UART has an independent power on reset circuit so normally it does not need an external reset source If BR11 is closed any system reset will temora rily remove the USB de...

Page 27: ...ins PH 4 6 The decoder chip IC4 activates one of it s eight low active outputs depending on the Port H pattern This provides an economical way to provide up to eight chip selects with a small number o...

Page 28: ...es a large number of general pur pose I O pins it may be desireable for some applications to keep a number of ports unused This is especially the case if the external bus interface is intended to be u...

Page 29: ...e set up SPI mode SPI0CR1 BM_SPE BM_MSTR CPOL 0 CPHA 0 latch input data PTH S12CO_SPICS4 PTH S12CO_SPICSH serialize latched data PTH S12CO_SPICS3 abyte xferSPI0 0 PTH S12CO_SPICSH return abyte Real Ti...

Page 30: ...egno UINT8 result set up SPI mode enable master CPOL 1 CPHA 1 LSB first SPI0CR1 BM_SPE BM_MSTR BM_CPOL BM_CPHA BM_LSBFE transfer data PTH S12CO_SPICS0_RD enable CS0 reading xferSPI0 regno send registe...

Page 31: ...AIN0 AIN7 The lower limit is ground 0V After opening solder bridge BR9 an external reference voltage can be used instead of IC10 note influence on DAC IC12 The analog inputs AIN0 to AIN7 as well as th...

Page 32: ...ivering 0V The DAC is controlled via SPI0 SPICS1 serves as chip select signal for the DAC The analog outputs VOUTA and VOUTB are available at connec tor X4 The following listing shows a software examp...

Page 33: ...14 is connected to SPI1 thus being independent from RTC ADC DAC etc which are using SPI0 The SPI1 signals MISO1 MOSI1 SCK1 and the chip select signal SS1 are provided by the MCU s port pins PH0 PH3 No...

Page 34: ...upt driven scheme should be preferred See AppNote AN2318 and accompanying software Hard External pull ups on SDA and SCL required Value should be 1k 5k depending on cap bus load Note Adjust IBFD value...

Page 35: ...er done CAUTION no loop time limit implemented stat IBSR BM_RXAK mask ACK status 0 ACK IBSR BM_IBIF clear IB Intr Flag return stat Func Receive byte from IIC Args ack IIC_ACK IIC_NOACK Retn byte recei...

Page 36: ...no physical drivers are provided on the S12compact They can be added externally if required TTL signals f r CAN1 to CAN3 are available at Port M Please refer to the schematic diagram to see if other f...

Page 37: ...e are going to use four 16 bit acceptance filters CAN0IDAC 0x10 set up acceptance filter and mask register 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE xxx xx...

Page 38: ...BM_TXE0 initiate transfer Bus Interface The MCU ports A B K and partly E are related to the Multiple xed External Bus Interface MEBI On the S12compact all bus signals are accessible via two header co...

Page 39: ...immediately after reset The monitor functions are described in a seperate document D Bug12 Reference Guide see product CD Startup Code Every Microcontroller firmware starts with a number of hardware...

Page 40: ...byte of the microcontroller s resour ces the type of memory does not matter However for write accesses some rules have to be followed Flash and EEPROM have to be erased before any write attempt Progr...

Page 41: ...t the end of the 64KB memory address range which falls within the protected monitor code space Therefore the application program can not modify the interrupt vectors directly To provide an alternative...

Page 42: ...3F8E dc w TP_RAMTOP 114 CAN0 receive FFB4 3F91 dc w TP_RAMTOP 111 CAN0 errors FFB6 3F94 dc w TP_RAMTOP 108 CAN0 wake up FFB8 3F97 dc w TP_RAMTOP 105 FLASH FFBA 3F9A dc w TP_RAMTOP 102 EEPROM FFBC 3F9...

Page 43: ...ndled by a line buffer Valid ASCII codes are in the range from 20 to 7E Backspace 08 will delete the character left of the cursor The ENTER key 0A is used to conclude the input The monitor prompt alwa...

Page 44: ...fy memory areas which can only be changed on a word by word basis Flash EEPROM In such cases the monitor always awaits and uses 16 bit data To exit the interactive mode simply type Q Additional comman...

Page 45: ...12 starts at 0x080000 0x20 16KB and ends at 0x0FFFFF 0x40 16 KB 1 Before loading into non volatile memory EEPROM Flash this kind of memory must always be erased Also only word writes can be used in th...

Page 46: ...e Flash memory ex monitor code space will be erased after user confirmation To remove erase the monitor code a BDM tool such as ComPOD12 StarProg is required Erase EEPROM Syntax Y sadr Erase one secto...

Page 47: ...FF 0800 1KB of total 4KB EEPROM the area below 0400 is hidden by control registers the top 2048 bytes by the RAM 07FF 0400 Control Registers 03FF 0000 Ressource End Begin Note Due to a mask set erratu...

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