PC6-TANGO • CompactPCI
®
PlusIO • Intel® Atom™ E39xx Processor (APL-I SoC)
1)
Various PCI control signals pulled up with 1k
S
to V(I/O). This resistor value is specified for +5V
V(I/O) but works as well with +3.3V V(I/O) under all environments which have been tested by
EKF. On request, 2.7k
S
P/U resistors can be stuffed.
2)
GA pins and some other signals are not connected
3)
SYSEN# is pulled up with 10k
S
to +3.3V
4)
Signals terminated by P/U resistors, but not in use
5)
PPS (pulse per second) and PPM (pulse per minute) as defined by IEEE 1588. These signals are
derived from NIC1 (I210IT), and must be enabled by GPIO27 of the APL-I SoC, since this
feature is EKF proprietary. According to the CompactPCI® Serial specification the SGPIO pins
(i.e. PPM/PPS when enabled) are distributed via the CompactPCI® Serial backplane, and
therefore can be used on a suitable peripheral card for triggering events. If a CompactPCI®
Serial peripheral card makes use of the SGPIO sideband signals, the PPS/PPM signals should be
disabled on the PC6-TANGO.
6)
As an exclusive stuffing option J2-C15 can be utilised as PSON# output
7)
The J2 backplane SATA port is available as an option, together with the on-board Marvell
88SE9170 SATA controller. Since the CompactPCI® PlusIO specification refers to SATA 3Gbps,
the Marvell SATA controller will be initialized for 3G operation. On request, the PC6-TANGO is
available with 6Gbps data rate for J2 SATA, but should be validated by the customer for the
targeted environment.
8)
PRST# is pulled up with 1k
S
to +3.3V. This is normally an input, for optional connection to
a push button (manual reset actuator). As an option, this pin may be reconfigured as RST#
output (platform reset). This will be required for applications which address PCI Express®
peripheral devices only via the rear I/O backplane connector J2, e.g. RIO modules such as the
PR1-RIO. A similar situation arises as result of an optional PC6-TANGO stand-alone
configuration, where the backplane connector J1 has been replaced by a +5V terminal block.
While J1 is present, RST# would be available on pin J1 C5. Without J1 however, the RST#
output must be derived from J2 C17 as an alternate. Hence, if J1 is not populated on the
PC6-TANGO, backplane slots which are based on PCI Express® (typically configured according
to CompactPCI® Serial) must be connected to J2/P2 C17 as platform reset.
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