PC6-TANGO • CompactPCI
®
PlusIO • Intel® Atom™ E39xx Processor (APL-I SoC)
LAN Subsystem
The Ethernet LAN subsystem is comprised of up to four Gigabit Ethernet ports. Two Intel® i210IT
Gigabit Ethernet controllers are provided to support the front panel RJ45 jacks (backwards compatible
to 10Base-T and 100Base-TX). Another two i210IT NICs are available as an option, for rear I/O usage
via the J2 backplane connector. Each port includes the following features:
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1000Base-Tx (Gigabit Ethernet), 100Base-TX (Fast Ethernet) and 10Base-T (Classic Ethernet)
capability
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Half- or full-duplex operation
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IEEE 802.3u, 802.3ab Auto-Negotiation for the fastest available connection
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Jumperless configuration (complete software-configurable)
Two bicoloured LEDs integrated into the dedicated RJ-45 connector in the front panel are used to
signal the LAN link, the LAN connection speed and activity status. A further bicoloured LED in front
panel labelled EB displays the state of the optional backplane network ports.
Due to limited internal resources of the APL, each GbE NIC device is connected via its PCI Express®
lane to an on-board PCI Express® 1:5 port packet switch (Diodes PI7C9X2G606PR), thus sharing a
common PCIe Gen2 lane (5Gbps) from the APL-I SoC. With its 5Gbps uplink, the PCIe switch can
smoothly control all four GbE NICs simultaneously at maximum networking speed. However, across
its remaining downstream port the PCIe switch would also feed an optional on-board SATA 6G
controller. For applications which use this hardware configuration intensely, a loss in networking
performance may temporarily occur.
The MAC addresses (unique hardware number assigned to any Ethernet NIC) are stored in dedicated
FLASH/EEPROM components.
The Intel Ethernet software and drivers for the i210IT are available for download from Intel®.
Any of the i210IT controllers supports the IEEE 1588 Precision Time Protocol, important for TSN (Time
Sensitive Networking) applications. In addition, the first NIC (which is connected to the upper RJ45
jack within the front panel) is configured to generate Pulse per Second (PPS) and Pulse per Minute
(PPM) signals for output via the jumper J-GP and to the backplane connector J2. These signals can be
used to trigger events on external hardware such as mezzanine side boards or peripheral cards. The
following routing can be enabled by UEFI/BIOS settings:
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Pulse per Second (PPS): J-GP Pin 1 and CompactPCI
®
J2 (signal SATA-SCL J2-D14)
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Pulse per Minute (PPM): CompactPCI
®
J2 (signal SATA-SDO J2-D13)
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