User Guide • PC3-ALLEGRO • CompactPCI
®
PlusIO CPU Board • Intel® i7-3xxx Processor
Main Memory
The PC3-ALLEGRO features two channels of DDR3 SDRAMs with support of ECC (Error Correction
Code). One channel is realized with 18 memory devices soldered to the board (Memory Down) and
delivers a capacity of up to 8GB with a clock frequency of 1600MHz (PC3-12800).
The 2nd channel provides a socket for installing a 204-pin ECC SODIMM module thus allowing a
simple expansion of system memory (max. module height = 1.25 inch). Supported are unbuffered
DDR3 ECC SODIMMs (72-bit) with V
DD
=1.5V featuring on-die termination (ODT), according the
PC3-12800 specification. Minimum module size is 512MB; maximum module size is 8GB. Please note
that standard DDR3 SODIMMs without ECC feature do not work on PC3-ALLEGRO.
It is recommended to add a SODIMM module with same size as the Memory Down to get best
performance (some of the system memory is dedicated to the graphics controller). This typically results
in a size of 2x4GB of memory which is recommended to run the operating systems Windows® Vista
or Windows® 7.
The memory controller supports symmetric and asymmetric memory organization. The maximum
memory performance can be obtained by using the symmetric mode. When in this mode, the memory
controller accesses the memory channels in an interleaved way. Since Core
TM
i7 processors support
Intels Flex Memory Technology, interleaved operation isn't limited to systems using memory channels
of equal capacity. In the case of unequal memory population the smaller memory channel dictates the
address space of the interleaved accessible memory region. The remainder of the memory is then
accessed in non-interleaved mode.
In asymmetric mode the memory always will be accessed in a non-interleaved manner with the
drawback of less bandwidth. The only meaningful application of asymmetric mode is the special case
when only one memory channel is populated (i.e. the SODIMM socket may be left empty).
The contents of the SPD EEPROM on the SODIMM is used by the BIOS at POST (Power-on Self Test) to
get any necessary timing parameters to program the memory controller within the chipset.
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